XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
xr
REV. 1.1.1
.
TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS
REG
READ/
WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
COMMENT
A2-A0
NAME
16C550 Compatible Registers
0 0 0
0 0 0
0 0 1
RHR
THR
RD
Bit-7
Bit-7
0/
Bit-6
Bit-6
0/
Bit-5
Bit-5
0/
Bit-4
Bit-4
0/
Bit-3
Bit-3
Bit-2
Bit-2
Bit-1
Bit-1
Bit-0
Bit-0
WR
IER RD/WR
Modem RXLine
Stat.
Int.
TX
Empty
Int
RX
Data
Int.
Stat.
Int.
CTS Int. RTS Int. Xoff Int.
Enable Enable Enable
Sleep
Mode
Enable
Enable Enable Enable Enable
LCR[7] = 0
0 1 0
ISR
RD
FIFOs
FIFOs
0/
0/
INT
INT
INT
INT
Enabled Enabled
Source Source Source Source
INT
INT
Bit-3
Bit-2
Bit-1
Bit-0
Source Source
Bit-5
Bit-4
0 1 0
0 1 1
FCR
WR RXFIFO RXFIFO
Trigger Trigger
0
0
DMA
Mode
TX
FIFO
RX
FIFOs
FIFO Enable
Enable Reset Reset
LCR RD/WR Divisor Set TX Set Par-
Even
Parity Enable
Parity
Stop
Bits
Word
Length Length
Bit-1 Bit-0
Word
Enable
Break
ity
1 0 0
1 0 1
MCR RD/WR
0/
0/
0/
Internal OP2#
Lopback Output
Enable Control
Rsvd
RTS# DTR#
Output Output
Control Control
(OP1#)
BRG
Pres-
caler
IR Mode XonAny
ENable
LSR
RD
RD
RX FIFO THR &
Global
Error
THR
Empty
RX
RX
RX
RX
RX
TSR
Empty
Break
Fram- Parity Over-
Data
LCR ≠ 0xBF
ing
Error
Error
run
Ready
Error
1 1 0
1 1 1
MSR
CD#
Input
RI#
Input
DSR#
Input
CTS#
Input
Delta
CD#
Delta
RI#
Delta
Delta
DSR# CTS#
SPR RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
Baud Rate Generator Divisor
0 0 0
0 0 1
0 1 0
DLL RD/WR
DLM RD/WR
Bit-7
Bit-7
Bit-6
Bit-6
Rsvd
Bit-5
Bit-5
Rsvd
Bit-4
Bit-4
Rsvd
Bit-3
Bit-3
Rsvd
Bit-2
Bit-2
Bit-1
Bit-1
Bit-0
Bit-0
LCR[7] = 1
LCR ≠ 0xBF
RXRDY# Baudout# Concur-
AFR RD/WR Rsvd
Select
Bit-2
0
Select
Bit-1
1
rent Write
Bit-0
0
0 0 0
0 0 1
DREV
DVID
RD
RD
Bit-7
0
Bit-6
0
Bit-5
0
Bit-4
0
Bit-3
0
LCR[7]=1
LCR ≠ 0xBF
DLL=0x00
DLM=0x00
22
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