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XRD5408AIP 参数 Datasheet PDF下载

XRD5408AIP图片预览
型号: XRD5408AIP
PDF下载: 下载PDF文件 查看货源
内容描述: 5V ,低功耗,电压输出串行8月10日/ 12-位DAC系列 [5V, Low Power, Voltage Output Serial 8/10/12-Bit DAC Family]
分类和应用: 转换器数模转换器光电二极管
文件页数/大小: 16 页 / 929 K
品牌: EXAR [ EXAR CORPORATION ]
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XRD5408/10/12
DAC
n
SDIN
MSB
X
X
X
X
DOUT
Figure 6. Shift Register Format
The DACs are programmed by a 16 bit word of serial data.
The format of the serial input register is shown in Figure 6.
The leading 4 bits are not used to update the DAC. If the
DAC is not daisy-chained then only a 12 bit serial word is
needed to program the DAC. The next 8, 10 or 12 bits
after the 4 leading bits are data bits. The XRD5408’s first
8 bits are valid data and the trailing 4 bits must be set to 0.
Figure 7
demonstrates the 16 bit digital word for the 8,
10,12 bit DACs.
Leading
Unused
Bits
XXXX
XXXX
XXXX
Data Bits
MSB
LSB
XXXXXXXX
XXXXXXXX
XXXXXXXX
Trailing
“0”
Bits
None
00
0000
--
+
AC
FT
Feedthrough (DAC Code = 0)
AC Feedthrough from V
REFIN
to V
OUT
is minimized with
low impedance grounding as shown in
Figure 7.
If the
DAC data is set to all “0”s then V
OUT
is a function of the
divider between the DAC string impedance and ground
impedance. See the Power Supply and Grounding
section for recommendations.
The typical AC
feedthrough for a 1kHz 2Vpp signal with code = 0 is
-80dB.
V
REFIN
XRD5408/10/12
R
IN
Part
XRD5412
XRD5410
XRD5408
Table 2. 16-Bit Digital Word Register for XRD5408,
XRD5410, XRD5412.
SCLK should be held low when CS transitions low. Data is
clocked in on the rising edge of SCLK when CS is low.
SDIN data is held in a 16 bit serial shift register. The DAC
is updated with the data bits on the rising edge of CS.
When CS is high data is not shifted into the
XRD5408/10/12.
Daisy-Chaining
The digital output port (DOUT) has a 4mA drive for greater
fan-out capability when daisy-chaining. DOUT allows
cascading of multiple DACs with the same serial data
stream. The data at SDIN appears at DOUT after 16 clock
cycles plus one clock width (t
CH
) and a propagation delay
(t
DO
). DOUT remains in the state of the last data bit when
CS is high. DOUT changes on the falling edge of SCLK
when CS is low.
Any number of DACs can be connected in this way by
connecting DOUT of one DAC to SDIN of the next DAC.
Rev. 1.20
9
GND
V
OUT
RGND
Analog GND
Figure 7. AC
FT
Feedthrough Equivalent
Circuit, DAC Code =0
Compatible with MAX515 & MAX539
The XRD5408/10/12 family of DACs are functionally
campatible with the MAX515 & MAX539 while providing
significant improvements. The XRD5408/10/12 DACs
have lower power, faster serial ports, and a constant
reference impedance to minimize the reference driving
requirements and maximize system linearity. The DOUT