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ST16C650A
2.90V TO 5.5V UART WITH 32-BYTE FIFO
REV. 5.0.0
4.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY ............................................................................ 25
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ......................................................................... 25
4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE .......................................................................... 25
4.3.1 IER versus Receive FIFO Interrupt Mode Operation ............................................................................... 25
4.3.2 IER versus Receive/Transmit FIFO Polled Mode Operation.................................................................... 26
4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ............................................................................ 27
4.4.1 Interrupt Generation: ................................................................................................................................ 27
4.4.2 Interrupt Clearing: .................................................................................................................................... 27
4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ............................................................................... 28
TABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL............................................................................................................................... 28
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ................................................................................ 29
TABLE 10: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION WITH AUTO RTS HYSTERESIS....................................................... 29
TABLE 11: PARITY SELECTION................................................................................................................................................................ 30
4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE ....... 31
4.8 LINE STATUS REGISTER (LSR) - READ ONLY ..................................................................................... 32
4.9 EXTRA FEATURE REGISTER (XFR) - WRITE ONLY .............................................................................. 33
4.10 MODEM STATUS REGISTER (MSR) - READ ONLY ............................................................................. 34
4.11 INFRARED TRANSMIT PULSE WIDTH CONTROL REGISTER (IRPW) - WRITE ONLY ............................. 35
4.12 SCRATCH PAD REGISTER (SPR) ..................................................................................................... 35
4.13 BAUD RATE GENERATOR DIVISORS (DLL AND DLM) - READ/WRITE ................................................. 35
4.14 DEVICE IDENTIFICATION REGISTER (DVID) - READ ONLY ................................................................. 35
4.15 DEVICE REVISION REGISTER (DREV) - READ ONLY ......................................................................... 35
4.16 ENHANCED FEATURE REGISTER (EFR) ............................................................................................ 35
TABLE 12: SOFTWARE FLOW CONTROL FUNCTIONS ............................................................................................................................... 36
4.17 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE ............... 37
TABLE 13: UART RESET CONDITIONS ............................................................................................................................................. 38
ELECTRICAL CHARACTERISTICS................................................................................ 39
DC ELECTRICAL CHARACTERISTICS ........................................................................................................... 39
AC ELECTRICAL CHARACTERISTICS ........................................................................................................... 40
TA=0O TO 70OC (-40O TO +85OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 2.90V TO 5.5V, 70 PF LOAD
WHERE APPLICABLE40
FIGURE 16. CLOCK TIMING .................................................................................................................................................................... 42
FIGURE 17. MODEM INPUT/OUTPUT TIMING............................................................................................................................................ 42
FIGURE 18. DATA BUS READ TIMING IN INTEL BUS MODE WITH AS# TIED TO GND................................................................................. 43
FIGURE 19. DATA BUS WRITE TIMING IN INTEL BUS MODE WITH AS# TIED TO GND ............................................................................... 43
FIGURE 20. DATA BUS READ TIMING IN INTEL BUS MODE USING AS#..................................................................................................... 44
FIGURE 21. DATA BUS WRITE TIMING IN INTEL BUS MODE USING AS# ................................................................................................... 44
FIGURE 22. DATA BUS READ TIMING IN PC MODE ................................................................................................................................. 45
FIGURE 23. DATA BUS WRITE TIMING IN PC MODE................................................................................................................................ 45
FIGURE 24. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] ................................................................................................... 46
FIGURE 25. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] ................................................................................................. 46
FIGURE 26. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED].................................................................................. 47
FIGURE 27. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] .................................................................................. 47
FIGURE 28. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] ..................................................................... 48
FIGURE 29. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] ...................................................................... 48
PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 MM) ................................................................................. 49
PACKAGE DIMENSIONS (44 PIN PLCC) ...................................................................................................... 50
REVISION HISTORY.................................................................................................................................... 51
TABLE OF CONTENTS ................................................................................................................................. I
II
EXAR [ EXAR CORPORATION ]
