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ST16C1550/51
2.97V TO 5.5V UART WITH 16-BYTE FIFO
REV. 4.2.0
FIGURE 16. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED]
Stop
Bit
Start
Bit
Last Data Byte
Transmitted
TX FIFO
Empty
TX
T
S
S
S
S
T
D0:D7
T
S
D0:D7
T
D0:D7
T
D0:D7
T
D0:D7
S
D0:D7
T
INT Cleared*
TSI
TSRT
INT*
TX FIFO
Empty
TX FIFO drops
below trigger level
TX FIFO above trigger
level and IER[1] enabled.
TXRDY
(ISR bit-4)
Data in
TX FIFO
TWT
IOW#
(Loading data
into FIFO)
*INT is cleared when the ISR is read and IER[1] is disabled.
TXDMA#
FIGURE 17. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED]
Stop
Bit
Start
Bit
Last Data Byte
Transmitted
TX
S
D0:D7
S
D0:D7
S
S
D0:D7
T
T
T
D0:D7
D0:D7
S
D0:D7
T
S D0:D7
T
T
INT cleared*
TSI
TSRT
INT*
TX FIFO drops
below trigger level
TX FIFO above trigger
level and IER[1] enabled.
TXRDY
(ISR bit-4)
At least 1
empty location
in FIFO
TX FIFO
Full
TWT
IOW#
(Loading data
into FIFO)
*INT cleared when the ISR is read and IER[1] is disabled.
TXDMA
31
EXAR [ EXAR CORPORATION ]
