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ST16C1550/51
2.97V TO 5.5V UART WITH 16-BYTE FIFO
REV. 4.2.0
FIGURE 12. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE]
RX
Stop
Bit
Start
Bit
D0:D7
D0:D7
D0:D7
TSSR
TSSR
TSSR
1 Byte
1 Byte
1 Byte
in RHR
in RHR
in RHR
INT
TSSR
TSSR
TSSR
Active
Data
Ready
Active
Data
Ready
Active
Data
Ready
RXRDY
(ISR bit-5)
TRR
TRR
TRR
IOR#
(Reading data
out of RHR)
RXNFM
FIGURE 13. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE]
TX
(Unloading)
Stop
Bit
Start
Bit
D0:D7
D0:D7
D0:D7
IER[1]
enabled
IER[1]
enabled
IER[1]
enabled
INT cleared*
INT cleared*
INT cleared*
INT*
TSRT
TSRT
TSRT
TXRDY
(ISR bit-4)
TWT
TWT
TWT
IOW#
(Loading data
into THR)
*INT is cleared when the ISR is read and IER[1] is disabled.
TXNonFIFO
29
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