ST16C1550/51
2.97V TO 5.5V UART WITH 16-BYTE FIFO
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REV. 4.2.0
FIGURE 14. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED]
Start
Bit
RX
S
S
S
S
S
T
S
D0:D7
D0:D7
D0:D7
T
D0:D7
TSSI
D0:D7
T
T
T
D0:D7
D0:D7
Stop
Bit
RX FIFO drops
below RX
Trigger Level
INT
RX FIFO fills up to RX
Trigger Level or RX Data
Timeout
TSSR
FIFO
Empties
First Byte is
Received in
RX FIFO
RXRDY
(ISR bit-5)
TRRI
TRR
IOR#
(Reading data out
of RX FIFO)
RXINTDMA#
FIGURE 15. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED]
Start
Bit
Stop
Bit
RX
S
S
S
S
T
D0:D7
T
T
S
T
S
T
D0:D7
D0:D7
D0:D7
D0:D7
TSSI
D0:D7
D0:D7
RX FIFO drops
below RX
Trigger Level
INT
RX FIFO fills up to RX
Trigger Level or RX Data
Timeout
TSSR
FIFO
Empties
RXRDY
(ISR bit-5)
TRRI
TRR
IOR#
(Reading data out
of RX FIFO)
RXFIFODMA
30
EXAR [ EXAR CORPORATION ]
