MP8799
Analog Input Multiplexer
Reference Voltages
The input/output relationship is a function of VREF
:
The MP8799 includes a 8-Channel analog input multiplexer.
The relationship between the clock, the multiplexer address, the
WR and the output data is shown in Figure 10.
AIN = VIN – VREF(–)
VREF = VREF(+) – VREF(–)
DATA = 1023 (AIN/VREF
)
A system can increase total gain by reducing VREF
.
Digital Interfaces
Clock
Sample N
Sample M
New Address
Sample
M+1
Old Address
The logic encodes the outputs of the comparators into a bi-
nary code and latches the data in a D-type flip-flop for output.
t
t
t
CLKH2
CLKS2
WR
WR
The functional equivalent of the MP8799 (Figure 12.) is com-
posed of:
t
AS
t
AH
1) Delay stage (tAP) from the clock to the sampling phase
(φS).
Address
2) An ideal analog switch which samples VIN.
3) An ideal A/D which tracks and converts VIN with no
delay.
N-1 Valid
Old Address
N Valid
Old Address
M Valid
New Address
DB0-DB9
N-2 Valid
4) A series of two DFF’s with specified hold (tHLD) and
delay (tDL) times.
t
= t
CLKH2
= 0
CLKS2
Figure 10. MUX Address Timing
tAP, tHLD and tDL are specified in the Electrical Characteristics
table.
φ S
V
IN
A/D
D Q
D Q
DB9-DB0
CLK
t
AS
t
AH
t
AP
A2, A1, A0
WR
MP8799
t
WR
CLK
N
N+1
N-1
t
MUXEN1
MUXEN
(Internal Signal)
V
IN
t
HLD
t
DL
DB9-DB0
N
Figure 11. Analog MUX Timing
Figure 12. MP8799 Functional Equivalent
Circuit and Interface Timing
Rev. 3.00
9
EXAR [ EXAR CORPORATION ]
