MP8799
Figure 7.
gives a visual definition of the INL error. The chart
shows a 3-bit converter transfer curve with greatly exaggerated
DNL errors to show the deviation of the real transfer curve from
the ideal one.
After a tester has measured all the transition voltages, the
computer draws a line parallel to the ideal transfer line. By defi-
nition the best fit line makes equal the positive and the negative
INL errors. For example, an INL error of –1 to +2 LSB’s relative
to the Ideal Line would be +1.5 LSB’s relative to the best fit line.
Output
Codes
7
Real Transfer Line
6
5
INL
4
3
2
1
LSB
Ideal Transfer Line
EFS
DATA
b. Single sampling
N
A system will clock the MP8799 continuously or it will give
clock pulses intermittently when a conversion is desired. The
timing of
Figure 8a
shows normal operation, while the timing of
Figure 8b
keeps the MP8799 in balance and ready to sample the
analog input.
CLOCK
DATA
N
N+1
N
a. Continuous sampling
N+1
Best Fit Line
CLOCK
N
BALANCE
Figure 8. Relationship of Data to Clock
Analog Input
The MP8799 has very flexible input range characteristics.
The user may set V
REF(+)
and V
REF(–)
to two fixed voltages and
then vary the input DC and AC levels to match the V
REF
range.
Another method is to first design the analog input circuitry and
then adjust the reference voltages for the analog input range.
One advantage is that this approach may eliminate the need for
external gain and offset adjust circuitry which may be required
by fixed input range A/Ds.
The MP8799’s performance is optimized by using analog in-
put circuitry that is capable of driving the A
IN
input.
Figure 9.
shows the equivalent circuit for A
IN
.
40
Ω
R Series
40W
A
IN
15 pF
R MUX
500W
87 pF
EZS
Analog Input (Volt)
Figure 7. INL Error Calculation
Clock and Conversion Timing
AV
DD
φ
S
60 pF
87 pF
160
Ω
4
1 pF
8
10 pF
300
Ω
φ
S
φ
B
+
4 pF
1/2 [ V
REF(+)
+ V
REF(–)
]
Control
Channel
Selection
Figure 9. Analog Input Equivalent Circuit
Rev. 3.00
8
EXAR [ EXAR CORPORATION ]
