n0_bus1_p
n0_bus1_n
n0_bus0_p
n0_bus0_n
h0_bus1_p
h0_bus1_n
h0_bus0_p
h0_bus0_n
Network-Side
SerDes/SGMII
(Port 0)
Host-Side
SerDes/SGMII
(Port 0)
srefclk_n
srefclk_p
SerDes/SGMII
Clock &
Termination
n1_bus1_p
n1_bus1_n
n1_bus0_p
n1_bus0_n
serdes_rref
Network-Side
SerDes/SGMII
(Port 1)
h_vtt
n_vtt
h1_bus1_p
h1_bus1_n
h1_bus0_p
h1_bus0_n
Host-Side
SerDes/SGMII)
(Port 1)
sdclk_fb_i
sdclk_fb_o
sdclk_diff_n
sdclk_diff_p
cs_n
ras_n
cas_n
we_n
DDR2
Memory
Interface
(Optional
IKE/SA
rmii_ref_clk
rmii_bus1_[2]
rmii_bus1_[1:0]
rmii_bus0_[2]
rmii_bus0_[1:0]
RMII
Control
Interface
ba[2:0]
a[13:0]
dqs[3:0]
Memory)
dm[3:0]
dq[31:0]
prefclk
pll_bypass
pll_mode_[1]
vssa_pll
ecc[6:0]
ecc_dm
eccs
PLL
(core)
odt
vdda_pll
testmode
por_n
Miscellaneous
Signals
jtag_tclk
jtag_tdi
host_config[2:0]
net_config[1:0]
JTAG
Interface
jtag_tdo
jtag_tms
jtag_rst_n
dpu_gpio[7:0]
esc_gpio[7:0]
General
Purpose I/O
Figure 6-2. 4450 I/O Signals (Second half of drawing)
4450 – Data Sheet, DS-0131-06
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