6 Signal Description
6.1 Signal Overview
n0_clk_1
n0_ctrl_1
h0_ctrl_1
h0_ctrl_0
Network-Side
n0_bus1[3:0]
RGMII/RTBI
h0_clk_2
n0_clk_0
(Port 0)
h0_clk_1
n0_ctrl_0
Host-Side
GMII/TBI/RGMII/
RTBI
n0_bus0[3:0]
h0_clk_0
vref
h0_bus1[9]
h0_bus1[8]
h0_bus1[7:0]
h0_bus0[9]
h0_bus0[8]
h0_bus0[7:0]
(Port 0)
h1_ctrl_1
h1_ctrl_0
n1_clk_1
n1_ctrl_1
Network-Side
RGMII/RTBI
(Port 1)
n1_bus1[3:0]
h1_clk_2
n1_clk_0
h1_clk_1
n1_ctrl_0
Host-Side
GMII/TBI/RGMII/
RTBI
h1_clk_0
n1_bus0[3:0]
h1_bus1[9]
h1_bus1[8]
h1_bus1[7:0]
h1_bus0[9]
h1_bus0[8]
h1_bus0[7:0]
(Port 1)
Figure 6-1. 4450 I/O Signals (First half of drawing)
Note
Depending on Ethernet interface configuration mode selected (Section 6.2), not all of the
interface pins may be used. Refer to the specific diagrams in the appropriate sections
below (Section 6.2.1 - 6.2.3).
4450 – Data Sheet, DS-0131-06
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