XR16C2850
SYMBOL DESCRIPTION
Symbol
Pin
44
Signal
type
Pin Description
40
48
A0
28
31
30
29
28
I
I
I
I
Address-0 Select Bit. - Internal register address selection.
Address-1 Select Bit. - Internal register address selection.
Address-2 Select Bit. - Internal register address selection.
A1
27
26
27
26
A2
-CS A-B
14,15 16,17 10,11
Chip Select A, B (active low) - This function is associated
with individual channels, A through B. These pins enable
data transfers between the user CPU and the 2850 for the
channel(s) addressed. Individual UART sections (A, B) are
addressed by providing a logic 0 on the respective -CS A-
B pin.
D0-D7
1-8
20
2-9
22
44-48
1-3
I/O
Data Bus (Bi-directional) - These pins are the eight bit, three
state data bus for transferring information to or from the
controlling CPU. D0 is the least significant bit and the first
data bit in a transmit or receive serial data stream.
GND
17
Pwr
O
Signal and power ground.
INT A-B
30,29 33,32 30,29
Interrupt A, B (three state) - This function is associated with
individual channel interrupts, INT A-B. INT A-B are enabled
when MCR bit-3 is set to a logic 1, interrupts are enabled in
the interrupt enable register (IER), and when an interrupt
condition exists. Interrupt conditions include: receiver er-
rors, available receiver buffer data, transmit buffer empty,
or when a modem status flag is detected.
-IOR
21
18
24
20
19
15
I
I
Read strobe (active low strobe) - A logic 0 transition on this
pin will load the contents of an Internal register defined by
address bits A0-A2 onto the 2850 data bus (D0-D7) for
access by an external CPU.
-IOW
Write strobe (active low strobe) - A logic 0 transition on this
pin will transfer the contents of the data bus (D0-D7) from
the external CPU to an internal register that is defined by
address bits A0-A2.
Rev. 1.00P
4
EXAR [ EXAR CORPORATION ]
