EtronTech
EM6AA160
Figure 35. Self Refresh Mode
tCK
Clock must be stable before
Exiting Self Refresh mode
tCH
tCL
CK
CK
tIS tIH
tIS
tIS
CKE
tIS tIH
NOP
VALID
COMMAND
NOP
AR
tIS tIH
VALID
ADDR
DQS
DQ
DM
tXSNR/
tXSRD**
tRP*
Enter Self Refresh
mode
Exit Self Refresh
mode
* = Device must be in the All banks idle state prior to entering Self Refresh mode
** = tXSNR is required before any non-READ command can be applied, and tXSRD (200 cycles of CK) is
required before a READ command can be applied.
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Etron Confidential
54
Rev. 1.3
Mar. /2014