Etr onTech
D.C. Characteristics
Parameter & Test Condition
4Mx32 DDR SDRAM
EM6A9320
4
5
(V
DD
= 2.8V
±
5% for 350, 333, 300, or 285MHz, V
DD
=2.5
±
5% for 250 or 200MHz, T
A
= 0~70
°C)
Symbol
2.8 3.0 3.3 3.5
Max
Unit Notes
OPERATING CURRENT :
One bank; Active-Precharge;
t
RC
=t
RC
(min); t
CK
=t
CK
(min); DQ,DM and DQS inputs
changing once per clock cycle; Address and control inputs
changing once every two clock cycles.
OPERATING CURRENT :
One bank; Active-Read-
Precharge; BL=4; CL=4; tRCDRD=4*t
CK
; t
RC
=t
RC
(min);
t
CK
=t
CK
(min); lout=0mA; Address and control inputs
changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT:
All banks idle; power-down mode; t
CK
=t
CK
(min);
CKE=LOW
IDLE STANDLY CURRENT :
CKE = HIGH;
CS#=HIGH(DESELECT); All banks idle; t
CK
=t
CK
(min);
Address and control inputs changing once per clock cycle;
V
IN
=V
REF
for DQ, DQS and DM
ACTIVE POWER-DOWN STANDBY CURRENT :
one
bank active; power-down mode; CKE=LOW; t
CK
=t
CK
(min)
ACTIVE STANDBY CURRENT :
CS#=HIGH;CKE=HIGH;
one bank active ; t
RC
=t
RC
(max);t
CK
=t
CK
(min);Address and
control inputs changing once per clock cycle;
DQ,DQS,and DM inputs changing twice per clock cycle
OPERATING CURRENT BURST READ :
BL=2; READS;
Continuous burst; one bank active; Address and control
inputs changing once per clock cycle; t
CK
=t
CK
(min);
lout=0mA;50% of data changing on every transfer
OPERATING CURRENT BURST Write :
BL=2; WRITES;
Continuous Burst ;one bank active; address and control
inputs changing once per clock cycle; t
CK
=t
CK
(min);
DQ,DQS,and DM changing twice per clock cycle; 50% of
data changing on every transfer
AUTO REFRESH CURRENT :
t
RC
=t
RFC
(min);
t
CK
=t
CK
(min)
SELF REFRESH CURRENT:
Sell Refresh Mode ;
CKE<=0.2V;t
CK
=t
CK
(min)
BURST OPERATING CURRENT 4 bank operation:
Four bank interleaving READs; BL=4;with Auto Precharge;
t
RC
=t
RC
(min); t
CK
=t
CK
(min); Address and control
inputschang only during Active, READ , or WRITE
command
IDD0
330 320 280 260 180 160 mA
IDD1
450 440 380 360 260 240 mA
IDD2P
50
50
50
50
45
40 mA
IDD2N 100 100 100 100
80
80 mA
IDD3P
50
50
50
50
45
40 mA
IDD3N 140 135 120 110 100 100 mA
IDD4R 560 540 480 450 440 420 mA
IDD4W 470 450 400 370 300 270 mA
IDD5
IDD6
430 430 420 410 300 280 mA
4
4
4
4
3
3 mA
IDD7
920 890 780 720 650 550 mA
Note:
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent
damage of the device.
2. All voltages are referenced to V
SS
.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate
under the minimum value of t
CK
and t
RC
. Input signals are changed one time during t
CK
.
4. Power-up sequence is described in previous page.
Etron Confidential
9
Rev 0.3
July. 2002
ETRON [ ETRON TECHNOLOGY, INC. ]
