Etr onTech
CK
t
RCDRD
t
RAS
t
RC
CMD
ACT
ROW ADR
RA
ROW ADR
BA
Bank ADR
RD
PRE
Percharge
t
RP
4Mx32 DDR SDRAM
EM6A9320
Figure 3. Bank Activate Read or Write Command Timing
t
RCDWR
t
RAS
t
RRD
ACT
ACT
WR
t
RC
PRE
ACT
t
RP
A0-11
CA
Column ADR
BA
BA
RA
RA
CA
RA
BA0-1
BA
BA
BA
BA
BA
Figure 4. Burst Stop for Read (CAS Letancy = 5, Burst Length = 4)
CK#
CK
CMD
RD
0
1
2
3
4
5
6
7
8
BST
Burst Stop for CAS Latency = 5
CMD
A0-11,
BA0-1
DQS
Valid
After 1 x CK Command can be
1x CK
DQ
DQ0 DQ1
Figure 5. Read with Auto Precharge (CAS Letancy = 5, Burst Length = 4)
CK#
CK
0
1
2
3
4
5
6
Read with Auto Precharge
CMD
RDA
CAS Latency = 5
A0-11,
BA0-1
DQS
Begin of Auto Precharge
DQ
Valid
Bank can be Active after Auto Precharge
ACT
Valid
t
RP
DQ0 DQ1 DQ2 DQ3
Etron Confidential
13
Rev 0.3
July. 2002
ETRON [ ETRON TECHNOLOGY, INC. ]
