Etr onTech
CL = 3
CL = 4
CL = 5
3.3
2.86
2.86
0.45
0.45
-0.6
-0.6
-
0.9
0.4
0.85
0
0.35
0.4
0.4
0.4
0.9
0.9
0.35
0.35
tCLMIN
or
tCHMIN
tHP -
0.35
20
22
14
7
5
6
4
3
2
1
1
9
200
tIS +
2tCK
-
4Mx32 DDR SDRAM
EM6A9320
4.0
Min
4
4
4
0.45
0.45
-0.7
-0.7
-
0.9
0.4
0.85
0
0.35
0.4
0.4
0.4
0.9
0.9
0.45
0.45
tCLMIN
or
tCHMIN
tHP -
0.45
15
17
10
5
3
3
3
3
2
1
2
8
200
tIS +
2tCK
-
Max
10
10
5
0.55
0.55
0.7
0.7
0.4
1.1
0.6
1.15
-
-
0.6
0.6
0.6
-
-
-
-
-
-
-
-
100K
-
-
-
-
-
-
-
-
-
-
-
7.8
Min
5
5
5
0.45
0.45
-0.7
-0.7
-
0.9
0.4
0.85
0
0.35
0.4
0.4
0.4
1.0
1.0
0.5
0.5
tCLMIN
or
tCHMIN
tHP -
0.5
12
14
8
4
2
3
2
2
2
1
2
7
200
tIS +
2tCK
5.0
Max
10
10
10
0.55
Unit
Electrical Characteristics and Recommended A.C. Operating Conditions
(V
DD
= 2.8V
±
5% for 350, 333, 300, or 285MHz, V
DD
=2.5
±
5% for 250 or 200MHz, T
A
= 0~70
°C)
2.8
3.0
3.3
3.5
Symbol
Parameter
Min Max Min Max Min Max Min Max
t
CK
Clock cycle time
10
10
5
0.55
0.55
0.6
0.6
0.35
1.1
0.6
1.15
-
-
0.6
0.6
0.6
-
-
-
-
-
-
-
-
100K
-
-
-
-
-
-
-
-
-
-
-
7.8
3.3
3.0
3.0
0.45
0.45
-0.6
-0.6
-
0.9
0.4
0.85
0
0.35
0.4
0.4
0.4
0.9
0.9
0.35
0.35
tCLMIN
or
tCHMIN
tHP -
0.35
20
22
14
7
5
6
4
3
2
1
1
9
200
tIS +
2tCK
-
10
10
5
0.55
0.55
0.6
0.6
0.35
1.1
0.6
1.15
-
-
0.6
0.6
0.6
-
-
-
-
-
-
-
-
100K
-
-
-
-
-
-
-
-
-
-
-
7.8
3.3
3.3
3.3
0.45
0.45
-0.6
-0.6
-
0.9
0.4
0.85
0
0.35
0.4
0.4
0.4
0.9
0.9
0.35
0.35
tCLMIN
or
tCHMIN
tHP -
0.35
17
19
12
6
4
5
3
3
2
1
1
9
200
tIS +
2tCK
-
10
10
5
0.55
0.55
0.6
0.6
0.35
1.1
0.6
1.15
-
-
0.6
0.6
0.6
-
-
-
-
-
-
-
-
100K
-
-
-
-
-
-
-
-
-
-
-
7.8
3.5
3.5
3.5
0.45
0.45
-0.6
-0.6
-
0.9
0.4
0.85
0
0.35
0.4
0.4
0.4
0.9
0.9
0.4
0.4
tCLMIN
or
tCHMIN
tHP -
0.4
16
18
11
5
3
3
3
3
2
1
1
9
200
tIS +
2tCK
10
10
5
0.55
0.55
0.6
0.6
0.4
1.1
0.6
1.15
-
-
0.6
0.6
0.6
-
-
-
-
-
-
-
-
100K
-
-
-
-
-
-
-
-
-
-
-
7.8
ns
Clock high level width
t
CH
Clock low level width
t
CL
t
DQSCK
DQS-out access time from CK,CK#
Output access time from CK,CK#
t
AC
DQS-DQ Skew
t
DQSQ
Read preamble
t
RPRE
Read postamble
t
RPST
CK to valid DQS-in
t
DQSS
t
WPRES
DQS-in setup time
t
WPREH
DQS-in hold time
DQS write postamble
t
WPST
DQS in high level pulse width
t
DQSH
DQS in low level pulse width
t
DQSL
Address and Control input setup time
t
IS
Address and Control input hold time
t
IH
DQ & DM setup time to DQS
t
DS
DQ & DM hold time to DQS
t
DH
t
CK
0.55
t
CK
0.7
ns
0.7
ns
0.45
ns
1.1
t
CK
0.6
t
CK
1.15
t
CK
-
ns
-
ns
0.6
t
CK
0.6
t
CK
0.6
t
CK
-
ns
-
ns
-
ns
-
ns
-
-
-
t
HP
t
QH
t
RC
t
RFC
t
RAS
t
RCDRD
t
RCDWR
t
RP
t
RRD
tw
R
t
CDLR
t
CCD
t
MRD
t
DAL
t
XSA
t
PDEX
t
REF
Clock half period
Output DQS valid window
Row cycle time
Refresh row cycle time
Row active time
RAS# to CAS# Delay in Read
RAS# to CAS# Delay in Write
Row precharge time
Row active to Row active delay
Write recovery time
Last data in to Read command
Col. Address to Col. Address delay
Mode register set cycle time
Auto precharge write recovery + Precharge
Self refresh exit to read command delay
Power down exit time
Refresh interval time
ns
ns
t
CK
-
t
CK
100K
t
CK
-
t
CK
-
t
CK
-
t
CK
-
t
CK
-
t
CK
-
t
CK
-
t
CK
-
t
CK
-
t
CK
-
t
CK
-
7.8
ns
us
Etron Confidential
11
Rev 0.3
July. 2002
ETRON [ ETRON TECHNOLOGY, INC. ]
