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EM68C08CWAE-3H 参数 Datasheet PDF下载

EM68C08CWAE-3H图片预览
型号: EM68C08CWAE-3H
PDF下载: 下载PDF文件 查看货源
内容描述: [128M x 8 bit DDRII Synchronous DRAM (SDRAM)]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 63 页 / 512 K
品牌: ETRON [ ETRON TECHNOLOGY, INC. ]
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EtronTech  
EM68C08CWAE  
Figure 47. Self refresh operation  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
Tm  
Tn  
tCK  
tCH  
tCL  
CK#  
CK  
>=tXSNR  
tRP*  
>=tXSRD  
CKE  
VIH(ac)  
VIL(ac)  
tIS  
tAOFD  
tIS  
VIL(ac)  
ODT  
CMD  
tIS  
tIH  
tIS  
tIH  
tIS tIH  
VIH(ac)  
VIL(ac)  
VIH(dc)  
VIL(dc)  
Self  
Refresh  
NOP  
NOP  
NOP  
Valid  
NOTE 1 Device must be in the "All banks idle" state prior to entering Self Refresh mode.  
NOTE 2 ODT must be turned off tAOFD before entering Self Refresh mode, and can be  
turned on again when tXSRD timing is satisfied.  
NOTE 3 tXSRD is applied for Read or a Read with autoprecharge command.  
t
XSNR is applied for any command except a Read or a Read with autoprecharge command.  
Figure 48. Basic power down entry and exit timing diagram  
CK  
CK#  
tIH  
tIS  
tIS tIH  
tIH  
tIS  
tIH  
CKE  
VALID  
or NOP  
VALID  
NOP  
NOP  
NOP  
VALID  
Command  
tCKE min  
tXP, tXARD  
tCKE(min)  
tXARDS  
Exit Power-Down mode  
Enter Power-Down mode  
Don't Care  
Figure 49. CKE intensive environment  
CK#  
CK  
tCKE  
tCKE  
CKE  
tCKE  
tCKE  
NOTE: DRAM guarantees all AC and DC timing & voltage specifications and proper DLL operation with intensive CKE operation  
Rev. 1.3  
57  
Oct. /2015  
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