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EM68C08CWAE-3H 参数 Datasheet PDF下载

EM68C08CWAE-3H图片预览
型号: EM68C08CWAE-3H
PDF下载: 下载PDF文件 查看货源
内容描述: [128M x 8 bit DDRII Synchronous DRAM (SDRAM)]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 63 页 / 512 K
品牌: ETRON [ ETRON TECHNOLOGY, INC. ]
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EtronTech  
EM68C08CWAE  
Figure 25. Seamless burst read operation: RL=5, AL=2, CL=3, BL=4  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
CK#  
CK  
Post CAS#  
READ A  
Post CAS#  
READ B  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
CMD  
DQS  
DQS#  
AL=2  
CL=3  
RL=5  
Dout A0 Dout A1 Dout A2 Dout A3 Dout B0 Dout B1 Dout B2  
DQs  
NOTE : The seamless burst read operation is supported by enabling a read command at every other clock for BL =  
4 operation, and every 4 clock for BL =8 operation. This operation is allowed regardless of same or different banks  
as long as the banks are activated.  
Figure 26. Read burst interrupt timing: (CL=3, AL=0, RL=3, BL=8)  
CK#  
CK  
Read A  
Read B  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
CMD  
DQS  
DQS#  
A0  
A1  
A2  
A3  
B0  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
DQs  
NOTE 1: Read burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited.  
NOTE 2: Read burst of 8 can only be interrupted by another Read command. Read burst interruption by Write  
command or Precharge command is prohibited.  
NOTE 3: Read burst interrupt must occur exactly two clocks after previous Read command. Any other Read burst  
interrupt timings are prohibited.  
NOTE 4: Read burst interruption is allowed to any bank inside DRAM.  
NOTE 5: Read burst with Auto Precharge enabled is not allowed to interrupt.  
NOTE 6: Read burst interruption is allowed by another Read with Auto Precharge command.  
NOTE 7: All command timings are referenced to burst length set in the mode register. They are not referenced to  
actual burst. For example, Minimum Read to Precharge timing is AL+BL/2 where BL is the burst length set in the  
mode register and not the actual burst (which is shorter because of interrupt).  
Rev. 1.3  
45  
Oct. /2015  
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