EM68932DVKB
EtronTech
TEMPERATURE COMPENSATED SELF REFRESH
In order to reduce power consumption, a Mobile DDR SDRAM includes the internal temperature sensor
and other circuitry to control Self Refresh operation automatically according to two temperature ranges:
max. 40°C and max. 85°C
Table 7. IDD6 Specifications and Conditions
Self Refresh Current (IDD6
)
Temperature Range
Full Array
200
1/2 of Full Array
1/4 of Full Array
Unit
µA
150
110
120
90
Max. 40°C
Max. 85°C
160
µA
PARTIAL ARRAY SELF REFRESH
For further power savings during Self Refresh, the PASR feature allows the controller to select the amount
of memory that will be refreshed during Self Refresh. The refresh options are all banks (banks 0, 1, 2 and
3); two banks (bank 0 and 1); and one bank (bank 0). Write and Read commands can still affect any bank
during standard operations, but only the selected banks will be refreshed during Self Refresh. Data in
unselected banks will be lost.
z Bank Activation / Row Address Command
The Bank Activation / Row Address command, also called the Active command, is issued by holding
CAS
and
High with
and
CS RAS
Low at the rising edge of the clock (CK). The DDR SDRAM has four
WE
independent banks, so two Bank Select Addresses (BA0, BA1) are required. The Active command must be
applied before any read or write operation is executed. The delay from the Active command to the first
Read or Write command must meet or exceed the minimum of
to
delay time (tRCD min). Once a
CAS
RAS
bank has been activated, it must be precharged before another Active command can be applied to the
same bank. The minimum time interval between interspersed Active commands (Bank 0 to Bank 3, for
example) is the bank to bank delay time (tRRD min).
z Burst Read Operation
Burst Read operation in a DDR SDRAM is initiated by asserting
and
Low while holding and
RAS
CS
RAS
High at the rising edge of the clock (CK) after tRCD from the Active command. The address inputs
WE
(A0~A7) determine the starting address for the Burst. The Mode Register sets the type of burst (Sequential
or Interleaved) and the burst length (2, 4, or 8). The first output data is available after the Latency
CAS
from the Read command, and the consecutive data bits are presented on the falling and rising edges of
Data Strobe (DQS) as supplied by the DDR SDRAM until the burst is completed.
z Burst Write Operation
The Burst Write command is issued by having CS , CAS and WE Low while holding RAS High at the
rising edge of the clock (CK). The address inputs determine the starting column address. There is no write
latency relative to DQS required for the Burst Write cycle. The first data for a Burst Write cycle must be
applied at the first rising edge of the data strobe enabled after tDQSS from the rising edge of the clock when
the Write command was issued. The remaining data inputs must be supplied on each subsequent falling
and rising edge of Data Strobe until the burst length is completed. After the burst has finished, any
additional data supplied to the DQ pins will be ignored.
Etron Confidential
10
Rev. 1.0
Aug. 2009
ETRON [ ETRON TECHNOLOGY, INC. ]
