EtronTech
Auto Refresh
EM68916DVAA
An Auto Refresh command is issued by having
CS
,
RAS
, and
CAS
held Low with CKE and
WE
High at the
rising edge of the clock (CK). All banks must be precharged and idle for a tRP (min) before the Auto Refresh
command is applied. The refresh addressing is generated by the internal refresh address counter. This makes
the address bits
“
Don’t Care
＂
during an Auto Refresh command. When the refresh cycle is complete, all
banks will be in the idle state. A delay between the Auto Refresh command and the next Active command or
subsequent Auto Refresh command must be greater than or equal to the t
RFC
(min).
Self Refresh
A Self Refresh command is defined by having
CS
,
RAS
,
CAS
and CKE Low with
WE
High at the rising
edge of the clock (CK). Once the Self Refresh command has been initiated, CKE must be held Low to keep
the device in Self Refresh mode. During the Self Refresh operation, all inputs except CKE are ignored. The
clock is internally disabled during Self Refresh operation to reduce power consumption. To exit the Self
Refresh mode, supply a stable clock input before returning CKE high, assert Deselect or a NOP command,
and then assert CKE high.
Power Down Mode
The device enters Power Down mode when CKE is brought Low, and it exits when CKE returns High. Once
the Power Down mode is initiated, all of the receiver circuits except CK and CKE are gated off to reduce
power consumption. All banks should be in an idle state prior to entering the Precharge Power Down mode
and CKE should be set high at least t
XP
prior to an Active command. During Power Down mode, refresh
operations cannot be performed; therefore the device must remain in Power Down mode for a shorter time
than the refresh period (t
REF
) of the device.
DEEP POWER DOWN
Deep Power Down achieves maximum power reduction by eliminating the power of the whole memory array
and surrounding circuitry. Data will not be retained in the memory storage array, the Mode Register, or the
Extended Mode Register once the device enters Deep Power Down mode.
This mode is entered by having all banks idle then
CS
and
WE
held Low with
RAS
and
CAS
held High at
the rising edge of the clock, while CKE is Low. This mode is exited by asserting CKE High, applying only
NOP commands for 200 microseconds, and then continuing with steps 4 through 11 of the Power Up and
Initialization sequence..
Etron Confidential
12
Rev. 1.0
Apr. 2009
ETRON [ ETRON TECHNOLOGY, INC. ]
