EtronTech
Write Interrupted by Write
EM68916DVAA
A Burst Write can be interrupted by the new Write command before completion of the previous Burst Write,
with the only restriction being that the interval that separates the commands must be at least one clock cycle.
When the previous burst is interrupted, the remaining addresses are overridden by the new addresses and
the new data will be written into the device until the programmed Burst Length is satisfied.
Write Interrupted by Read & DM
A Burst Write can be interrupted by a Read command to any bank. The DQ must be in the high impedance
state at least one clock cycle before the interrupting read data appears on the outputs to avoid data
contention. When the Read command is to be asserted, any residual data from the Burst Write sequence
must be masked by DM. The delay from the last data to the Read command (t
WTR
) is required to avoid data
contention inside the DRAM. Data presented on the DQ pins before the Read command is initiated will
actually be written to the memory. A Read command interrupting a write sequence can not be issued at the
next clock edge following the Write command.
Write Interrupted by Precharge & DM
A Burst Write can be interrupted by a Precharge of the same bank before completion of the previous burst. A
write recovery time (t
WR
) is required from the last data to the Precharge command. When the Precharge
command is asserted, any residual data from the Burst Write cycle must be masked by DM.
Burst Stop Command
The Burst Stop command is initiated by having
RAS
and
CAS
High with
CS
and
WE
Low at the rising edge
of the clock only. The Burst Stop command has the fewest restrictions, making it the easiest method to use
when terminating a burst operation before it has been completed. When the Burst Stop command is issued
during a Burst Read cycle, both the data and DQS (Data Strobe) go to a high impedance state after a delay
which is equal to the
CAS
latency set in the Mode Register. The Burst Stop command, however, is not
supported during a Burst Write operation.
DM Masking Function
The DDR SDRAM has a Data Mask function that can be used in conjunction with the data write cycle only, not
the read cycle. When the Data Mask is activated (DM High) during a write operation, the write data is masked
immediately (DM to Data Mask latency is zero). DM must be issued at the rising edge or the falling edge of
Data Strobe instead of at a clock edge.
Auto Precharge Operation
Auto Precharge is a feature which performs the same individual bank precharge function as described above,
but without requiring an explicit command. This is accomplished by using A10 (A10 = High), to enable Auto
Precharge in conjunction with a specific READ or WRITE command. A precharge of the bank / row that is
addressed with the READ or WRITE command is automatically performed upon completion of the read or
write burst. Auto Precharge is non persistent in that it is either enabled or disabled for each individual READ
or WRITE command. Auto Precharge ensures that a precharge is initiated at the earliest valid stage within a
burst. The user must not issue another command to the same bank until the precharging time (t
RP
) is
completed. When the Auto Precharge command is activated, the active bank automatically begins to
precharge at the earliest possible moment during a read or write cycle after t
RAS
(min) is satisfied.
Precharge Command
The Precharge command is issued when
CS
,
RAS
, and
WE
are Low and
CAS
is High at the rising edge of
the clock (CK). The Precharge command can be used to precharge any bank individually or all banks
simultaneously. The Bank Select addresses (BA0, BA1) are used to define which bank is precharged when
the command is initiated. For a write cycle, t
WR
(min) must be satisfied from the start of the last Burst Write
cycle until the Precharge command can be issued. After t
RP
from the precharge, an Active command to the
same bank can be initiated.
Etron Confidential
11
Rev. 1.0
Apr. 2009
ETRON [ ETRON TECHNOLOGY, INC. ]
