欢迎访问ic37.com |
会员登录 免费注册
发布采购

EM63A165TS-7IG 参数 Datasheet PDF下载

EM63A165TS-7IG图片预览
型号: EM63A165TS-7IG
PDF下载: 下载PDF文件 查看货源
内容描述: [16M x 16 bit Synchronous DRAM (SDRAM)]
分类和应用: 动态存储器光电二极管内存集成电路
文件页数/大小: 53 页 / 565 K
品牌: ETRON [ ETRON TECHNOLOGY, INC. ]
 浏览型号EM63A165TS-7IG的Datasheet PDF文件第15页浏览型号EM63A165TS-7IG的Datasheet PDF文件第16页浏览型号EM63A165TS-7IG的Datasheet PDF文件第17页浏览型号EM63A165TS-7IG的Datasheet PDF文件第18页浏览型号EM63A165TS-7IG的Datasheet PDF文件第20页浏览型号EM63A165TS-7IG的Datasheet PDF文件第21页浏览型号EM63A165TS-7IG的Datasheet PDF文件第22页浏览型号EM63A165TS-7IG的Datasheet PDF文件第23页  
EM63A165  
EtronTech  
Table 16. Electrical Characteristics and Recommended A.C. Operating Conditions  
±
(VDD = 3.3V 0.3V, TA = -40~85°C) (Note: 5, 6, 7, 8)  
-5I  
-6I  
-7I  
Symbol  
A.C. Parameter  
Row cycle time  
Unit Note  
Min. Max. Min. Max. Min. Max.  
tRC  
55  
55  
15  
-
-
-
60  
60  
18  
-
-
-
63  
63  
21  
-
-
-
(same bank)  
tRFC  
tRCD  
Refresh cycle time  
RAS# to CAS# delay  
(same bank)  
tRP  
Precharge to refresh/row activate command  
(same bank)  
21  
-
15  
-
18  
-
tRRD  
Row activate to row activate delay  
(different banks)  
10  
10  
40  
-
-
12  
12  
42  
-
-
14  
14  
42  
-
-
tMRD  
tRAS  
Mode register set cycle time  
Row activate to precharge time  
(same bank)  
120K  
120K  
120K  
tWR  
tCK  
Write recovery time  
10  
10  
5
-
12  
10  
6
-
-
14  
10  
7
-
ns  
9
CL* = 2  
-
-
Clock cycle time  
CL* = 3  
-
-
-
10  
10  
tCH  
tCL  
Clock high time  
Clock low time  
2
-
2
-
2.5  
2.5  
-
-
2
-
2
-
-
CL* = 2  
-
-
-
6
5
-
6
Access time from CLK  
10  
9
tAC  
(positive edge)  
CL* = 3  
-
4.5  
-
-
5.4  
tOH  
tLZ  
Data output hold time  
Data output low impedance  
Data output high impedance  
2
-
2.5  
0
2.5  
0
-
0
-
-
-
tHZ  
-
4.5  
-
5
-
-
5.4  
8
tIS  
Data/Address/Control Input set-up time  
Data/Address/Control Input hold time  
Power Down Exit set-up time  
1.5  
0.8  
-
-
1.5  
0.8  
1.5  
0.8  
-
-
10  
10  
tIH  
-
tPDE  
tREFI  
tXSR  
tIS+ CK  
t
-
tIS+ CK  
t
-
tIS+ CK  
t
-
Average Refresh interval time  
-
7.8  
-
-
7.8  
-
-
7.8  
-
µs  
ns  
Exit Self-Refresh to any Command  
tRC+ IS  
t
tRC+ IS  
t
tRC+tIS  
*
CL is CAS Latency.  
Note:  
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the  
device.  
2. All voltages are referenced to VSS. Overshoot VIH (Max) = 4.6V for pulse width 3ns. Undershoot VIL (Min) =  
-1.0V for pulse width 3ns.  
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the  
minimum value of tCK and tRC. Input signals are changed one time during every 2 tCK.  
4. These parameters depend on the output loading. Specified values are obtained with the output open.  
5. Power-up sequence is described in Note 11.  
6. A.C. Test Conditions  
Rev. 2.2  
19  
Dec. /2013  
 复制成功!