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EM638325TS-5/-5G 参数 Datasheet PDF下载

EM638325TS-5/-5G图片预览
型号: EM638325TS-5/-5G
PDF下载: 下载PDF文件 查看货源
内容描述: 2M ×32同步DRAM ( SDRAM ) [2M x 32 Synchronous DRAM (SDRAM)]
分类和应用: 动态存储器
文件页数/大小: 72 页 / 761 K
品牌: ETRON [ ETRON TECHNOLOGY, INC. ]
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EtronTech  
EM638325  
2Mega x 32 SDRAM  
11 Device Deselect command (CS# = "H")  
The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE#  
and Address inputs are ignored, regardless of whether the CLK is enabled. This command is similar  
to the No Operation command.  
12 AutoRefresh command  
(RAS# = "L", CAS# = "L", WE# = "H",CKE = "H", BS0,1 = Dont care, A0-A10 = Don't care)  
The AutoRefresh command is used during normal operation of the SDRAM and is analogous to  
CAS#-before-RAS# (CBR) Refresh in conventional DRAMs. This command is non-persistent, so it  
must be issued each time a refresh is required. The addressing is generated by the internal refresh  
controller. This makes the address bits a "don't care" during an AutoRefresh command. The internal  
refresh counter increments automatically on every auto refresh cycle to all of the rows. The refresh  
operation must be performed 4096 times within 64ms. The time required to complete the auto  
refresh operation is specified by tRC(min.). To provide the AutoRefresh command, all banks need to  
be in the idle state and the device must not be in power down mode (CKE is high in the previous  
cycle). This command must be followed by NOPs until the auto refresh operation is completed. The  
precharge time requirement, tRP(min), must be met before successive auto refresh operations are  
performed.  
13 SelfRefresh Entry command  
(RAS# = "L", CAS# = "L", WE# = "H", CKE = "L", A0-A10 = Don't care)  
The SelfRefresh is another refresh mode available in the SDRAM. It is the preferred refresh  
mode for data retention and low power operation. Once the SelfRefresh command is registered, all  
the inputs to the SDRAM become "don't care" with the exception of CKE, which must remain LOW.  
The refresh addressing and timing is internally generated to reduce power consumption. The  
SDRAM may remain in SelfRefresh mode for an indefinite period. The SelfRefresh mode is exited by  
restarting the external clock and then asserting HIGH on CKE (SelfRefresh Exit command).  
14 SelfRefresh Exit command  
(CKE = "H", CS# = "H" or CKE = "H", RAS# = "H", CAS# = "H", WE# = "H")  
This command is used to exit from the SelfRefresh mode. Once this command is registered,  
NOP or Device Deselect commands must be issued for tRC(min.) because time is required for the  
completion of any bank currently being internally refreshed. If auto refresh cycles in bursts are  
performed during normal operation, a burst of 4096 auto refresh cycles should be completed just  
prior to entering and just after exiting the SelfRefresh mode.  
15 Clock Suspend Mode Entry / PowerDown Mode Entry command (CKE = "L")  
When the SDRAM is operating the burst cycle, the internal CLK is suspended(masked) from the  
subsequent cycle by issuing this command (asserting CKE "LOW"). The device operation is held  
intact while CLK is suspended. On the other hand, when all banks are in the idle state, this command  
performs entry into the PowerDown mode. All input and output buffers (except the CKE buffer) are  
turned off in the PowerDown mode. The device may not remain in the Clock Suspend or PowerDown  
state longer than the refresh period (64ms) since the command does not perform any refresh  
operations.  
16 Clock Suspend Mode Exit / PowerDown Mode Exit command  
When the internal CLK has been suspended, the operation of the internal CLK is reinitiated from  
the subsequent cycle by providing this command (asserting CKE "HIGH"). When the device is in the  
PowerDown mode, the device exits this mode and all disabled buffers are turned on to the active  
state. tPDE(min.) is required when the device exits from the PowerDown mode. Any subsequent  
commands can be issued after one clock cycle from the end of this command.  
17 Data Write / Output Enable, Data Mask / Output Disable command (DQM = "L", "H")  
During a write cycle, the DQM signal functions as a Data Mask and can control every word of  
the input data. During a read cycle, the DQM functions as the controller of output buffers. DQM is  
also used for device selection, byte selection and bus control in a memory system.  
Preliminary  
15  
Rev 1.4  
Oct. 2005