EtronTech
EM638325
2Mega x 32 SDRAM
T0
T 1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CK2
CKE
CS#
Clock min.
RAS#
CAS#
WE#
Address Key
ADDR.
DQM
tRP
Hi-Z
DQ
Mode Register
Set Command
PrechargeAll
Any
Command
Mode Register Set Cycle (CAS# Latency = 2, 3)
The mode register is divided into various fields depending on functionality.
Address BS0,1 A10/AP A9
Function RFU* RFU* WBL Test Mode
*Note: RFU (Reserved for future use) should stay “0” during MRS cycle.
Burst Length Field (A2~A0)
A8
A7
A6
A5
A4
A3
BT
A2
A1
A0
CAS Latency
Burst Length
·
This field specifies the data length of column access using the A2~A0 pins and selects the Burst
Length to be 2, 4, 8, or full page.
A2
0
A1
0
A0
0
Burst Length
1
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
Reserved
Reserved
Reserved
Full Page
1
0
1
1
1
0
1
1
1
Preliminary
12
Rev 1.4
Oct. 2005
ETRON [ ETRON TECHNOLOGY, INC. ]
