EtronTech
EM638325
2Mega x 32 SDRAM
Electrical Characteristics and Recommended A.C. Operating Conditions
(VDD = 3.3V 0.3V, Ta = 0~70°C) (Note: 5, 6, 7, 8)
±
- 5/5.5/6/7/8/10
Min.
Symbol
A.C. Parameter
Max.
Unit Note
tRC
Row cycle time
(same bank)
9
55/55/60/70/80/100
10/11/12/14/16/20
tRRD
tRCD
Row activate to row activate delay
(different banks)
9
9
RAS# to CAS# delay
(same bank)
18/18/18/21/24/30
15/16.5/18/21/24/30
35/38.5/42/49/56/70
tRP
Precharge to refresh/row activate command
(same bank)
9
9
tRAS
Row activate to precharge time
(same bank)
100,000
tCK2
tCK3
tAC2
Clock cycle time
CL* = 2
CL* = 3
CL* = 2
-/-/10/10/ - / -
5/5.5/6/7/8/10
ns
Access time from CLK
-/-/6/6/-/-
9
tAC3
tOH
(positive edge)
CL* = 3
4.5/5/5.5/5.5/6/6
Data output hold time
2/2/2/2.5/2.5/2.5
9
tCH
tCL
tIS
Clock high time
Clock low time
2/2/2.5/3/3/3.5
10
10
10
10
9
2/2/2.5/3/3/3.5
Data/Address/Control Input set-up time
Data/Address/Control Input hold time
Data output low impedance
1.5/1.5/1.5/1.75/2/2.5
tIH
1
1
tLZ
tHZ2
tHZ3
tWR
Data output high impedance
CL* = 2
CL* = 3
-/-/6/6/-/-
4.5/5/5.5/5.5/6/6
8
Write recovery time
2
2/1/1/1/1/1
2
tCCD
tMRS
CAS# to CAS# Delay time
Mode Register Set cycle time
CLK
*
CL is CAS# Latency.
Note:
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device.
2. All voltages are referenced to VSS.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the
minimum value of tCK and tRC. Input signals are changed one time during tCK.
4. These parameters depend on the output loading. Specified values are obtained with the output open.
5. Power-up sequence is described in Note 11.
Preliminary
18
Rev 1.4
Oct. 2005
ETRON [ ETRON TECHNOLOGY, INC. ]
