EtronTech
EM638325
2Mega x 32 SDRAM
Figure 19.3. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
High
CKE
CS#
RAS#
CAS#
WE#
BS0,1
RBx
RBy
RBy
RAx
A10
RAx
CAx
RBx
CBx
A0~A9
DQM
DQ
Data is ignored
Hi-Z
DBx DBx+1
DBx+2
DAx+1
DBx+3
DAx DAx+1 DAx+2 DAx+3 DAx-1 DAx
DBx+4 DBx+5
Activate
Write
Activate
Command
Bank A
Write
Precharge
Activate
Command
Bank B
Command
Command
Command
Bank B
Command
Bank B
Bank B
Bank A
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Burst Stop
Command
Full Page burst operation does
not terminate when the burst
length is satisfied; the burst counter
increments and continues bursting
beginning with the starting address.
Preliminary
64
Rev 1.4
Oct. 2005