EtronTech
EM638325
2Mega x 32 SDRAM
Figure 15.2. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
RAx
RAx
RBw
RBw
CBw
CBx
CBy
CBz
CAx
CAy
A0~A9
DQM
tWR
tRCD
tRP
tRP
tRRD
Hi-Z
DAx0
DAx1 DAx2 DAx3DBw0 DBw1DBx0 DBx1DBy0 DBy1DAy0 DAy1 DBz0 DBz1
DBz2
DQ
DBz3
Activate
Command Command
Bank A Bank A
Write
Activate
Command
Bank B
Write
Command Command
Bank B Bank B
Write
Write
Command Command
Bank B Bank A
Write
Write
Command
Bank B
Precharge
Command
Bank B
Precharge
Command
Bank A
Preliminary
51
Rev 1.4
Oct. 2005
ETRON [ ETRON TECHNOLOGY, INC. ]
