EtronTech
EM638325
2Mega x 32 SDRAM
Figure 14.1. Interleaving Column Read Cycle (Burst Length=4, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK1
CS#
RAS#
CAS#
WE#
BS0,1
A10
RAx
RAx
RBw
RBw CBw
CBy
CBz
RAx
CBx
CAy
A0~A9
tRCD tAC1
DQM
DQ
Hi-Z
Bz2 Bz3
Ax0
Ax1 Ax2
Ax3 Bw0 Bw1 Bx0 Bx1
By0
By1 Ay0
Ay1 Bz0
Read
Bz1
Activate
Activate
Command
Bank B
Read
Command
Bank B
Read
Command Command
Bank B Bank A
Read
Precharge
Precharge
Command
Bank B
Command
Bank A
Command Command
Bank B
Bank A
Read
Read
Command
Bank B
Command
Bank A
Preliminary
47
Rev 1.4
Oct. 2005