EtronTech
EM636327
DQ
Column Address DQ Planes
DQ
Column Address DQ Planes
A0 Controlled
16~23
Inputs A2
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0 Controlled
Inputs A2
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
DQ0
DQ1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0~7
0~7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
16~23
16~23
16~23
16~23
16~23
16~23
16~23
24~31
24~31
24~31
24~31
24~31
24~31
24~31
24~31
DQ2
0~7
DQ3
0~7
DQ4
0~7
DQ5
0~7
DQ6
0~7
DQ7
0~7
DQ8
8~15
8~15
8~15
8~15
8~15
8~15
8~15
8~15
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
m
A block write access requires a time period of tBWC to execute, so in general, there should be
m
NOP cycles( equals (tBWC - tCK)/tCK rounded up to the next whole number), after the Block Write
command. However, BankActivate or BankPrecharge commands to the other bank are allowed.
When following a Block Write with a BankPrecharge or PrechargeAll command to the same bank,
tBPL must be met.
9
Write and AutoPrecharge command (refer to the following figure)
(RAS# = "H", CAS# = "L", WE# = "L", DSF = "L", BS = Bank, A9 = "H", A0-A7 = Column Address)
The Write and AutoPrecharge command performs the precharge operation automatically after
the write operation. Once this command is given, any subsequent command can not occur within a
time delay of {(burst length -1) + tWR + tRP(min.)}. At full-page burst, only the write operation is
performed in this command and the auto precharge function is ignored.
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Bank A
Activate
Write A
COMMAND
NOP
NOP
NOP
NOP
NOP
NOP
NOP
AutoPrecharge
DAL
t
CAS# latency=1
DIN
DIN
DIN
A
A
A
DIN A
DIN A
DIN A
0
0
0
1
1
1
*
*
*
t
, DQ's
CK1
tDAL
CAS# latency=2
, DQ's
t
CK2
tDAL
CAS# latency=3
, DQ's
t
CK3
Begin AutoPrecharge
Bank can be reactivated at completion of tDAL
tDAL= tWR + tRP
*
Burst Write with Auto-Precharge
(Burst Length = 2, CAS# Latency = 1, 2, 3)
Preliminary
1998
December
13