EM636327Q-6 参数 Datasheet PDF下载

EtronTech

DSF

BankActivate

command

D

CK

DQ7

MR7

DQ6

MR6

DQ5

MR5

DQ4

MR4

DQ3

MR3

DQ2

MR2

DQ1

MR1

DQ0

MR0

Q

DQM0

EM636327

DRAM

CELL

0 = Masked

1 = Not Masked

Note:

Only the lower byte is shown. The operation is identical for other bytes.

Write Per Bit (I/O Mask) Block Diagram

A write burst without the auto precharge function may be interrupted by a subsequent

Write/Block Write, BankPrecharge/PrechargeAll, or Read command before the end of the burst

length. An interrupt coming from Write/Block Write command can occur on any clock cycle

following the previous Write command (refer to the following figure).

T0

CLK

T1

T2

T3

T4

T5

T6

T7

T8

COMMAND

NOP

WRITE A

WRITE B

NOP

NOP

NOP

NOP

NOP

NOP

1 Clk Interval

DQ's

DIN A0

DIN B0

DIN B 1

DIN B2

DIN B3

Write Interrupted by a Write

(Burst Length = 4, CAS# Latency = 1, 2, 3)

The Read command that interrupts a write burst without auto precharge function should be

issued one cycle after the clock edge in which the last data-in element is registered. In order to

avoid data contention, input data must be removed from the DQs at least one clock cycle before the

Preliminary

10

December

1998