EtronTech
EM636165-XXI
1M x 16 SDRAM
Figure 19.3. Full Page Write Cycle
(Burst Length=Full Page, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
High
CKE
CS#
RAS#
CAS#
WE#
A11
RAx
RBx
RBx
RBy
RBy
A10
A0~A9
DQM
CBx
RAx
CAx
Data is ignored
Hi-Z
DBx DBx+1
Write
DAx+1
DBx+3
DBx+4 DBx+5
DQ
DAx DAx+1 DAx+2 DAx+3 DAx-1 DAx
DBx+2
Activate
Command
Bank A
Write
Command
Bank A
Precharge
Command
Bank B
Activate
Command
Bank B
Activate
Command
Bank B
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Full Page burst operation does
not terminate when the burst
length is satisfied; the burst counter
increments and continues bursting
beginning with the starting address.
Burst Stop
Command
Preliminary
65
Rev. 1.1 Apr. 2005
ETRON [ ETRON TECHNOLOGY, INC. ]
