EtronTech
EM636165-XXI
1M x 16 SDRAM
Figure 15.2. Interleaved Column Write Cycle
(Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RAx
RBw
RBw
CBw
CBx
CBy
CBz
CAx
CAy
A0~A9
DQM
tWR
tRCD
tRP
tRP
tRRD
DAx0
Hi-Z
DBz2
DBz3
DQ
DAx1 DAx2 DAx3DBw0 DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1 DBz0 DBz1
Activate
Write
Activate
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Write
Command Command
Bank B Bank A
Write
Write
Command
Bank B
Precharge
Command
Bank B
Command Command
Bank A
Bank A
Precharge
Command
Bank A
Preliminary
52
Rev. 1.1 Apr. 2005
ETRON [ ETRON TECHNOLOGY, INC. ]
