EtronTech
EM636165-XXI
1M x 16 SDRAM
Figure 14.3. Interleaved Column Read Cycle
(Burst Length=4, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCK3
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RAx
RBx
CAx RBx
CBx
CBz
CBy
CAy
A0~A9
DQM
tAC3
tRCD
Hi-Z
DQ
Ax0
Ax1 Ax2
Ax3 Bx0
Read
Bx1 By0 By1
Bz0 Bz1 Ay0 Ay1 Ay2 Ay3
Precharge
Command
Bank A
Activate
Command
Bank A
Read
Read
Command
Bank B
Read
Command
Bank B
Read Prechaerge
Command Command
Bank A Bank B
Command
Bank A
Command
Bank B
Activate
Command
Bank B
Preliminary
50
Rev. 1.1 Apr. 2005