Etr onTech
Symbol
Parameter
Min
Read Cycle
tRC
tAA
tCO1
tCO2
tOE
tBA
tLZ
tOLZ
tBLZ
tHZ
tOHZ
tBHZ
tOH
tWC
tWP
tAW
tCW
tBW
tAS
tWR
tWHZ
tOW
tDW
tDH
Read cycle time
Address access time
Chip Enable (CE1#) Access Time
Chip Enable (CE2) Access Time
Output enable access time
Data Byte Control Access Time
Chip Enable Low to Output in Low-Z
Output enable Low to Output in Low-Z
Data Byte Control Low to Output in Low-Z
Chip Enable High to Output in High-Z
Output Enable High to Output in High-Z
Data Byte Control High to Output in High-Z
Output Data Hold Time
Write Cycle
Write Cycle Time
Write Pulse Width
Address Valid to End of Write
Chip Enable to End of Write
Data Byte Control to End of Write
Address Setup Ttime
Write Recovery Time
WE# Low to Output in High-Z
WE# High to Output in Low-Z
Data to Write Overlap
Data Hold Time
85
60
70
70
70
0
0
−
5
30
0
−
−
−
−
−
−
−
30
−
−
−
70
50
60
60
60
0
0
−
5
30
0
85
−
−
−
−
−
10
5
10
−
−
−
10
−
85
85
85
40
85
−
−
−
35
35
35
−
70
−
−
−
−
−
10
5
10
−
−
−
10
-85
Max
Min
EM566168
-70
Max
AC Characteristics and Operating Conditions (Ta = -25°C to 85°C, VCC = 2.7V to 3.3V)
Unit
−
70
70
70
35
70
−
−
−
25
25
25
−
−
−
−
−
−
−
−
20
−
−
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC Test Condition
•
Output load : 50pF + one TTL gate
•
Input pulse level : 0.4V, 2.4
•
Timing measurements : 0.5 x VCC
•
tR, tF : 5ns
Preliminary
5
Rev 0.2
Feb. 2002