16 bit 模数转换器
TM7705
Calibration Limit14
Offset Calibration
Limit14
GAIN
Gain(1 to 128)
V max
V min
V max
GAIN Is the Selected PGA
Gain(1 to 128)
—(1.05×VREF
GAIN
)
Input Span15
GAIN Is the Selected PGA
Gain(1 to 128)
(0.8×VREF)/GAIN
(2.1×VREF)/GAIN
GAIN Is the Selected PGA
Gain(1 to 128)
POWER REQUIREMENTS
VDD Voltage
+2.7 to +3.3
Vmin to
Vmax
For Specified Performance
Digital I/Ps=0V or VDD.External
MCLK IN and CLK DIS=1
BUF Bit=O. fCLKIN=1MHz.Gains
of 1 to 128
0.32
mA max
mA max
mA max
mA max
mA max
mA max
0.6
BUF Bit=1. fCLKIN=1MHz.Gains
of 1 to 128
Power Supply
Currents16
0.4
BUF Bit=O.fCLKIN=2.4576MHz.
Gains of 1 to 4
0.6
BUF Bit=O. fCLKIN=2.4576MHz.
Gains of 8 to 128
0.7
BUF Bit=O. fCLKIN=2.4576MHz.
Gains of 1 to 4
1.1
BUF Bit=1. fCLKIN=2.4576MHz.
Gains of 8 to 128
+4.75 to +5.25
Vmin
For Specified Performance
VDD Voltage
toVmax
Digital I/Ps=0V or VDD.External
MCLK IN and CLK DIS=1.
BUF Bit=0. fCLKIN=1MHz.Gains
of 1 to 128
0.45
0.7
0.6
0.85
0.9
1.3
16
mA max
mA max
mA max
mA max
mA max
mA max
μA max
μA max
BUF Bit=1. fCLKIN=1MHz.Gains
of 1 to 128
Power
Supply
Currents16
BUF Bit=0. fCLKIN=2.4576MHz.
Gains of 1 to 4
BUF Bit=0. fCLKIN=2.4576MHz.
Gains of 8 to 128
BUF Bit=1. fCLKIN=2.4576MHz.
Gains of 1 to 4
BUF Bit=1. fCLKIN=2.4576MHz.
Gains of 8 to 128
External MCLK IN=0V or VDD.
VDD=5V.See Figure 9
Standby(Power-Dow
n)Current17
8
External MCLK IN=0V or VDD.
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www.titanmec.com
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