16 bit 模数转换器
TM7705
（VDD= +2.7V~+5.2V；GND=0V；fCLKIN =2.4567MHz；Input Logic 0=0 V，
Logic 1 = VDD 除非另有说明）
Limit at
Parameter
TMIN ,TMAX
Units
Conditions/Comments
(B Version)
Master Clock Frequency: Crystal
Oscillator or Externally Supplied
for Specified Performance
Master Clock Input Low Time.
tCLKIN=1/ fCLKIN
3,4
fCLKIN
400
2.5
kHzmin
MHz max
ns min
tCLKIN LO
0.4×tCLKIN
tCLKIN HI
0.4×tCLKIN
500×tCLKIN
100
ns min
ns mon
ns min
Master Clock Input High Time.
DRDY High Time
t1
t2
RESETPulsewidth
Read Operation
t3
0
ns min
ns min
DRDY to CS Setup Time
CS Falling Edge to SCLK Rising
Edge Setup Time
t4
120
5
t5
0
ns min
SCLK Falling Edge to Data Valid
Delay
80
ns max
ns max
ns min
ns min
VDD=+5V
VDD=+3.0V
SCLK High Pulsewidth
SCLK Low Pulsewidth
CS Rising Edge to SCLK Rising
Edge Hold Time
100
100
100
t6
t7
t8
t9
0
ns min
ns min
6
10
Bus RelinguishTimeafter SCLK
Rising Edge
60
ns max
ns max
ns max
VDD=+5V
100
100
VDD=+3.0V
SCLK Falling Edge to DRDY High7
t10
Write Operation
t11
t12
t13
120
ns min
ns min
ns min
CS Falling Edge to SCLK Rising
Edge Setup Time
30
Data Valid to SCLK Rising Edge
Setup Time
20
Data Valid to SCLK Rising Edge
Hold Time
t14
t15
t16
100
100
0
ns min
ns min
ns min
SCLK High Pulsewidth
SCLK High Pulsewidth
CS Rising Edge to SCLK Rising
Edge Hold Time
注释：
1. 样品测试温度为+25℃以保证一致性。所有的输入信号满足：tr =tf =5ns（VDD
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www.titanmec.com
-10-
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