ESMT
M52D32162A
Burst Read Single bit Write Cycle @ Burst Length = 2
C L O C K
* N o t e 1
H I G H
C K E
C S
RA S
* N o t e 2
CA S
CA a RB b CA b
RA a
C B c
A D D R
BA
R A c
CA d
A10/AP
RA a
R A c
RB b
CL= 2
DAa0
QAb0 QAb1
QAd0 QAd1
DBc 0
DBc 0
D Q
CL= 3
W E
QAb0 QAb1
QAd0 QAd1
DAa0
D Q M
Row A c t i ve
( A- B an k )
Rea d
( A- B an k )
Row A c t i ve
( A- B an k )
Pr e ch ar g e
( A- B an k )
Row Active
(B-Bank)
W r i t e wi t h
Read with
W r i t e
Au to Pr echar g e
( B- Ba nk )
Auto Precharge
(A-Bank)
( A - Ban k )
:D o n' t C ar e
*Note: 1. BRSW modes is enabled by setting A9 “High” at MRS (Mode Register Set).
At the BRSW Mode, the burst length at write is fixed to “1” regardless of programmed burst length.
2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated.
Auto precharge is executed at the next cycle of burst-end, so in the case of BRSW write command, the precharge
command will be issued after two clock cycles.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2009
Revision : 1.6 23/32
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
