ESMT
M52D32162A
Read & Write Cycle with auto Precharge @ Burst Length = 4
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C L O C K
C K E
H I G H
C S
RA S
C A S
A D D R
C b
R a
R b
C a
BA
A10/AP
R a
R b
CL= 2
D Q
Qa1 Qa2
Qa3
Qa2
Qa0
Db0
Db0
Db1
Db2
Db3
Db3
CL= 3
Qa1
Qa3
Qa0
Db1 Db2
W E
D Q M
Row Active
( A - Bank )
Read with
Auto Precharge
( A - Bank )
Auto Precharge
Start Point
( A - Bank)
W r i t e wi t h
Auto Pr echarge
( B- Bank )
Aut o Pr echarge
Star t Poin t
( B- Bank )
Row Active
( B - Bank )
: D o n ' t C a r e
*Note: 1.tCDL should be controlled to meet minimum tRAS before internal precharge start
(In the case of Burst Length=1 & 2 and BRSW mode)
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2009
Revision : 1.6 19/32
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
