ESMT
M52D32162A
Read & Write Cycle at Different Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
1 0
11
1 2
1 3
1 4
1 8
1 5
1 6
1 7
1 9
CLOCK
CKE
HIGH
tRRD
C S
R A S
CAS
ADDR
RAc
CAa
CBb
RAa
CAc
RBb
BA
RAa
RAc
RBb
A10/AP
CL=2
*Note1
t
CDL
QAa2 QAa3
DBb1
QAa1
QAa0
DBb0
DBb2
QAc0
QAa0
DBb3
QAc1
QAc2
DQ
QAa1
QAa2
DBb2 DBb3
QAc0 QAc1
CL=3
WE
QAa3
DBb0 DBb1
DQM
Write
(B-Bank)
Read
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
Row Active
(A-Bank)
Row Active
(B-Bank)
: D o n ' t C a r e
*Note: 1.tCDL should be met to complete write.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2009
Revision : 1.6 18/32