ESMT
M52D128168A (2E)
Power Up Sequence
13
14
15
16
17
18
19
20
0
1
2
3
4
5
6
7
8
9
11
12
10
C L O C K
C K E
H i g h l e v e l i s n e c e s s a r y
C S
t
R F C
t
R F C
t
R P
t
M R D
t
M R D
R A S
C A S
A D D R
K e y
K e y
R A
B A 1
B A 0
B S
B S
R A
A10/AP
H i g h - Z
D Q
W E
D QM
H i g h l e v e l i s n e c e s s a r y
M o d e R e g i s t e r S e t
A u t o R e f r e s h
A u t o R e f r e s h
P r e c h a r g e
( A l l B a n k s )
R o w A c t i v e
E x t e n d e d M o d e
R e g i s t e r S e t
:
D o n ' t c a r e
Power-Up and Initialization Sequence
The following sequence is required for POWER UP and Initialization.
1. Apply power and attempt to maintain CKE at a low state (all other inputs may be undefined.)
-
-
Apply VDD before or at the same time as VDDQ
Apply VDDQ
2. Start clock and maintain stable condition for a minimum.
3. The minimum of 200us after stable power and clock (CLK), apply NOP & take CKE high.
4. Issue precharge commands for all banks of the device.
5. Issue 2 or more auto-refresh commands.
6. Issue mode register set command to initialize the mode register.
7. Issue extended mode register set command to set PASR and DS.
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2012
Revision: 1.0
31/47
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
