ESMT
M52D128168A (2E)
FUNCTION TRUTH TABLE (TABLE2)
Current
State
CKE
( n-1 )
CKE
n
ADDR
ACTION
Note
CS RAS CAS WE
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
H
H
H
H
X
H
H
H
H
H
L
X
H
H
H
H
H
L
X
H
L
L
L
X
X
H
H
H
L
X
X
X
H
H
H
L
X
X
X
H
H
H
X
X
H
H
L
X
X
X
X
H
H
L
X
X
X
X
H
H
L
X
X
H
L
X
X
X
X
X
H
L
X
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
INVALID
Exit Self Refresh Æ Idle after tRFC (ABI)
Exit Self Refresh Æ Idle after tRFC (ABI)
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Maintain Self Refresh)
INVALID
Exit Self Refresh Æ ABI
Exit Self Refresh Æ ABI
ILLEGAL
6
6
Self
Refresh
L
X
X
H
L
L
L
All
Banks
Precharge
Power
7
7
ILLEGAL
ILLEGAL
Down
L
X
X
H
L
L
L
NOP (Maintain Low Power Mode)
Refer to Table1
Enter Power Down
Enter Power Down
ILLEGAL
H
L
L
L
L
8
8
All
Banks
Idle
X
ILLEGAL
H
L
L
L
H
H
RA
Row (& Bank) Active
H
H
L
H
H
L
L
L
L
H
L
H
L
L
L
L
L
L
L
H
L
X
Enter Self Refresh
Mode Register Access
NOP
Refer to Operations in Table 1
Begin Clock Suspend next cycle
Exit Clock Suspend next cycle
Maintain Clock Suspend
8
OP Code
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Any State
other than
Listed
9
9
above
L
Abbreviations: ABI = All Banks Idle, RA = Row Address
*Note: 6.CKE low to high transition is asynchronous.
7.CKE low to high transition is asynchronous if restart internal clock.
A minimum setup time 1CLK + tSS must be satisfy before any command other than exit.
8.Power down and self refresh can be entered only from the all banks idle state.
9.Must be a legal command.
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2012
Revision: 1.0 28/47
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
