ESMT
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS
Address
Function
BA0
0
BA1
0
A11~A10/AP
RFU
A9
W.B.L
A8~A7
TM
A6
A5
M52D128168A (2E)
A4
A3
BT
A2
A1
A0
CAS Latency
Burst Length
Test Mode
A8
0
0
1
1
A7
0
1
0
1
Type
Mode Register Set
Reserved
EMRS
Reserved
A6
0
0
0
0
1
1
1
1
CAS Latency
A5
0
0
1
1
0
0
1
1
A4
0
1
0
1
0
1
0
1
Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Burst Type
A3
0
1
Type
Sequential
Interleave
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
Burst Length
A0
0
1
0
1
0
1
0
1
BT = 0
1
2
4
8
BT = 1
1
2
4
8
Write Burst Length
A9
0
1
Length
Burst
Single Bit
Reserved Reserved
Reserved Reserved
Reserved Reserved
Full Page Reserved
Full Page Length: 512
Note:
1. RFU (Reserved for future use) should stay “0” during MRS cycle.
2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.
3. The full column burst (512 bit) is available only at sequential mode of burst type.
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2012
Revision: 1.0
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