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M14D5121632A-2.5BIG2H 参数 Datasheet PDF下载

M14D5121632A-2.5BIG2H图片预览
型号: M14D5121632A-2.5BIG2H
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 32MX16, 0.4ns, CMOS, PBGA84, 8 X 12.50 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, BGA-84]
分类和应用: 动态存储器双倍数据速率内存集成电路
文件页数/大小: 62 页 / 1001 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
M14D5121632A (2H)  
Operation Temperature Condition (TC) -40°C~95°C  
Current State  
Address  
Command  
DESEL  
Action  
CS RAS CAS  
WE  
X
H
L
L
L
L
L
L
L
H
L
X
H
H
H
L
X
H
L
X
X
NOP (Bank Active after tWR  
NOP (Bank Active after tWR  
ILLEGAL (*1, 6)  
)
H
H
L
NOP  
)
BA, CA, A10  
READ / READA  
WRITE / WRITEA  
Active  
L
BA, CA, A10  
WRITE / WRITEA  
WRITE  
RECOVERING  
H
H
L
H
L
BA, RA  
ILLEGAL (*1)  
L
BA, A10 / A10  
PRE / PREA  
Refresh  
ILLEGAL (*1) / ILLEGAL  
ILLEGAL  
L
H
L
X
L
L
Op-Code Mode-Add  
MRS / EMRS  
DESEL  
ILLEGAL  
X
H
X
H
X
X
X
NOP (Bank Active after tWR  
)
)
H
NOP  
NOP (Bank Active after tWR  
WRITE  
RECOVERING  
with  
READ / READA /  
WRITE / WRITEA  
L
H
L
X
BA, CA, A10  
ILLEGAL (*1)  
L
L
L
L
H
L
L
L
H
H
L
H
L
BA, RA  
Active  
ILLEGAL (*1)  
ILLEGAL (*1) / ILLEGAL  
ILLEGAL  
AUTO  
PRECHARGE  
BA, A10 / A10  
PRE / PREA  
Refresh  
L
H
L
X
L
L
Op-Code Mode-Add  
MRS / EMRS  
DESEL  
ILLEGAL  
X
H
X
H
X
H
X
X
NOP (Idle after tRFC  
)
)
NOP  
NOP (Idle after tRFC  
READ / READA /  
WRITE / WRITEA  
L
H
L
X
BA, CA, A10  
ILLEGAL  
REFRESH  
L
L
L
L
H
L
L
L
H
H
L
H
L
BA, RA  
Active  
ILLEGAL  
ILLEGAL  
ILLEGAL  
ILLEGAL  
BA, A10 / A10  
PRE / PREA  
Refresh  
L
H
L
X
L
L
Op-Code Mode-Add  
MRS / EMRS  
DESEL  
X
H
X
H
X
H
X
X
NOP (Idle after tMRD  
)
)
NOP  
NOP (Idle after tMRD  
READ / READA /  
WRITE / WRITEA  
L
H
L
X
BA, CA, A10  
ILLEGAL  
(Extended)  
MODE  
REGISTER  
SETTING  
L
L
L
L
L
L
L
L
H
H
L
H
L
BA, RA  
Active  
ILLEGAL  
ILLEGAL  
ILLEGAL  
ILLEGAL  
BA, A10 / A10  
PRE / PREA  
Refresh  
H
L
X
L
Op-Code Mode-Add  
MRS / EMRS  
H = High Level, L = Low level, X = Don’t Care  
BA = Bank Address, RA =Row Address, CA = Column Address, NOP = No Operation  
ILLEGAL = Device operation and / or data integrity are not guaranteed.  
Note:  
1. This command may be issued for other banks, depending on the state of the banks.  
2. All banks must be in “IDLE”.  
3. All AC timing specs must be met.  
4. Only allowed at the boundary of 4 bits burst. Burst interruption at other timings is illegal.  
5. Available in case tRCD is satisfied by AL setting.  
6. Available in case tWTR is satisfied.  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Aug. 2011  
Revision : 1.1 58/62  
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