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M14D5121632A-2.5BBG2A 参数 Datasheet PDF下载

M14D5121632A-2.5BBG2A图片预览
型号: M14D5121632A-2.5BBG2A
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 32MX16, 0.4ns, CMOS, PBGA84, BGA-84]
分类和应用: 动态存储器双倍数据速率内存集成电路
文件页数/大小: 64 页 / 1089 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT
DC Specifications
(IDD values are for the operation range of Voltage and Temperature)
Parameter
Symbol
Test Condition
M14D5121632A (2A)
Version
-1.5
-1.8
-2.5
Unit
Operating Current
(Active - Precharge)
IDD0
Operating Current
(Active - Read -
Precharge)
IDD1
Precharge
Power-Down
Standby Current
IDD2P
One bank;
t
CK
= t
CK
(IDD), t
RC
= t
RC
(IDD), t
RAS
= t
RAS
(IDD)min;
CKE is High, CS is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
One bank; I
OUT
= 0mA;
BL = 4, CL = CL(IDD), AL = 0;
t
CK
= t
CK
(IDD), t
RC
= t
RC
(IDD),
t
RAS
= t
RAS
(IDD)min, t
RCD
= t
RCD
(IDD);
CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
All banks idle;
t
CK
= t
CK
(IDD); CKE is LOW;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
All banks idle;
t
CK
= t
CK
(IDD); CKE is HIGH, CS is HIGH;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
All banks idle;
t
CK
= t
CK
(IDD); CKE is HIGH, CS is HIGH;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
All banks open;
Fast PDN Exit
t
CK
= t
CK
(IDD); CKE is LOW;
MRS(12) = 0
Other control and address bus inputs
Slow PDN Exit
are STABLE;
MRS(12) = 1
Data bus input are FLOATING
All banks open;
t
CK
= t
CK
(IDD), t
RAS
= t
RAS
(IDD)max, t
RP
= t
RP
(IDD);
CKE is HIGH, CS is HIGH between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
All banks open, continuous burst Reads, I
OUT
= 0mA;
BL = 4, CL = CL (IDD), AL = 0;
t
CK
= t
CK
(IDD), t
RAS
= t
RAS
(IDD)max, t
RP
= t
RP
(IDD);
CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data pattern is the same as IDD4W;
All banks open, continuous burst Writes;
BL = 4, CL = CL (IDD), AL = 0;
t
CK
= t
CK
(IDD), t
RAS
= t
RAS
(IDD)max, t
RP
= t
RP
(IDD);
CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
100
80
75
mA
130
100
95
mA
15
12
12
mA
Precharge Quiet
Standby Current
IDD2Q
60
40
40
mA
Idle Standby Current IDD2N
55
45
45
mA
45
30
35
20
35
mA
20
Active Power-down
Standby Current
IDD3P
Active Standby
Current
IDD3N
60
50
50
mA
Operation Current
(Read)
IDD4R
180
160
140
mA
Operation Current
(Write)
IDD4W
170
150
130
mA
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2016
Revision : 1.0
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