ESMT
M13S64164A
AC Operating Test Conditions
Parameter
Input reference voltage for clock (VREF
Input signal maximum peak swing
Input signal minimum slew rate
Input levels (VIH/VIL)
Value
Unit
)
0.5*VDDQ
V
V
1.5
1.0
V/ns
V
VREF+0.31/VREF-0.31
Input timing measurement reference level
Output timing reference level
VREF
VTT
V
V
AC Timing Parameter & Specifications
(VDD = 2.3V~2.7V, VDDQ=2.3V~2.7V, TA =0°C to 70°C )
-5
-6
Symbol
Unit
Parameter
min
max
min
max
CL2
CL2.5
CL3
7.5
12
7.5
6.0
6.0
-0.7
12
ns
ns
Clock Period
tCK
6.0
5.0
12
8
12
10
tAC
-0.7
+0.7
+0.7
Access time from CLK/ CLK
CLK high-level width
tCH
tCL
0.45
0.45
-0.6
0.75
0.45
0.45
1.75
0.75
0.75
0.8
0.55
0.45
0.45
-0.6
0.75
0.45
0.45
1.75
0.75
0.75
0.8
0.55
tCK
tCK
ns
tCK
ns
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
tCK
tCK
ns
CLK low-level width
0.55
0.55
Data strobe edge to clock edge
tDQSCK
tDQSS
tDS
+0.6
+0.6
Clock to first rising edge of DQS delay
Data-in and DM setup time (to DQS)
Data-in and DM hold time (to DQS)
DQ and DM input pulse width (for each input)
Input setup time (fast slew rate)
1.25
1.25
-
-
tDH
-
-
tDIPW
tIS
-
-
-
-
Input hold time (fast slew rate)
tIH
-
-
Input setup time (slow slew rate)
Input hold time (slow slew rate)
tIS
-
-
tIH
0.8
-
-
0.8
-
-
Control and Address input pulse width
DQS input high pulse width
tIPW
tDQSH
tDQSL
tDSS
tDSH
tDQSQ
2.2
2.2
0.4
0.6
0.6
-
0.4
0.6
0.6
-
DQS input low pulse width
0.4
0.4
DQS falling edge to CLK rising-setup time
DQS falling edge from CLK rising-hold time
Data strobe edge to output data edge
0.2
0.2
0.2
-
0.2
-
-
0.45
-
0.45
Data-out high-impedance window from
CLK/ CLK
tHZ
-0.7
-0.7
+0.7
+0.7
-0.7
-0.7
+0.7
+0.7
ns
ns
Data-out low-impedance window from
CLK/ CLK
tLZ
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2009
Revision : 1.4 6/48
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
