ESMT
M13S32321A (2G)
Timing Diagram
Basic Timing (Setup, Hold and Access Time @ BL=4, CL=2)
0
1
2
3
4
5
6
7
8
9
10
C L K
C L K
t
C H
t
C H
t
C L
t
C L
t
C K
t
C K
H IG H
C K E
t
I S
C S
t
I H
R A S
C A S
B A
A8 /AP
Ra
Ra
A D D R
( A 0 ~ A 7 , A 9 )
C b
Ca
W E
D Q S
D Q
t
R P S T
t
D Q S S
t
D Q S C K
t
D Q S C K
t
W P S T
t
D Q S L
H i - Z
H i - Z
t
R P R E
H i - Z
H i - Z
t
D Q S H
t
D Q S Q
t
WPREtDS
t
DH
DS
DH
t
tWPRES
t
A C
t
t
H Z
t
L Z
D b 3
Q a 0
Q a 1
Q a 2
Q a 3
D b 0 D b 1 D b 2
t
Q H
D M
READ
C O M M A N D
ACTIVE
WRITE
:
D o n ’ t c a r e
11 1 0 1 B 3 2 R . A
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2012
Revision : 1.0 31/48
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
