ESMT
Command Truth Table
COMMAND
Register
Register
Extended MRS
Mode Register Set
Auto Refresh
Refresh
Entry
Self
Refresh
Exit
L
H
H
Auto Precharge Enable
Auto Precharge Disable
H
Auto Precharge Enable
Burst Stop
Precharge
Bank Selection
All Banks
Entry
Exit
Entry
Precharge Power Down
Mode
Exit
DM
No Operation Command
L
H
H
X
H
L
H
H
H
H
L
H
X
X
L
H
L
L
L
H
L
X
H
L
H
L
H
L
X
V
X
X
H
X
V
X
X
H
X
H
X
H
H
H
X
V
X
X
H
X
V
L
L
X
V
X
X
H
X
V
X
X
X
X
X
X
L
H
L
L
X
CKEn-1 CKEn CS
H
H
H
X
X
H
L
H
X
X
L
H
L
L
H
X
L
H
H
X
H
L
H
X
H
H
X
X
X
L
L
L
RAS
L
L
L
CAS
L
L
L
WE
M13S128324A
DM
X
X
X
BA0,1
A8/AP
OP CODE
OP CODE
X
A11~A9,
A7~A0
Note
1,2
1,2
3
L
L
H
3
3
3
4
4
4
4,6
7
X
5
X
V
V
H
L
V
H
X
V
X
L
H
X
Row Address
L
Column
Address
Column
Address
Bank Active & Row Addr.
Read &
Column
Address
Write &
Column
Address
Auto Precharge Disable
Active Power Down
X
X
V
X
X
X
8
(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)
Note:
1. OP Code: Operand Code. A0~A11 & BA0~BA1: Program keys. (@EMRS/MRS)
2. EMRS/MRS can be issued only at all banks precharge state.
A new command can be issued 1 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by “Auto”.
Auto/self refresh can be issued only at all banks precharge state.
4. BA0~BA1: Bank select addresses.
If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.
If BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank B is selected.
If BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected.
5. If A8/AP is “High” at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t
RP
after end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampling at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2009
Revision : 2.3
8/50
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
