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M13S128324A_09 参数 Datasheet PDF下载

M13S128324A_09图片预览
型号: M13S128324A_09
PDF下载: 下载PDF文件 查看货源
内容描述: 1M ×32位×4银行双倍数据速率SDRAM [1M x 32 Bit x 4 Banks Double Data Rate SDRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 50 页 / 950 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT
DC Specifications
Parameter
Operation Current
(One Bank Active)
Operation Current
(One Bank Active)
Precharge Power-down
Standby Current
Idle Standby Current
Active Power-down Standby
Current
Active Standby Current
Operation Current (Read)
Operation Current (Write)
Auto Refresh Current
Self Refresh Current
Symbol
Test Condition
t
RC
= t
RC
(min) t
CK
= t
CK
(min)
Active – Precharge
Burst Length = 2 t
RC
= t
RC
(min),
CL= 2.5 I
OUT
= 0mA,
Active-Read- Precharge
CKE
V
IL
(max), t
CK
= t
CK
(min),
All banks idle
CKE
V
IH
(min), CS
V
IH
(min), t
CK
= t
CK
(min)
All banks ACT, CKE
V
IL
(max),
t
CK
= t
CK
(min)
One bank; Active-Precharge,
t
RC
= t
RAS
(max), t
CK
= t
CK
(min)
Burst Length = 2, CL= 2.5 ,
t
CK
= t
CK
(min), I
OUT
= 0mA
Burst Length = 2, CL= 2.5 ,
t
CK
= t
CK
(min)
t
RC
t
RFC
(min)
CKE
0.2V
-3.6
235
-4
210
M13S128324A
Version
-5
175
-6
145
Unit
Note
IDD0
mA
-
IDD1
245
220
190
180
mA
-
IDD2P
IDD2N
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
40
135
60
150
440
470
320
3
40
120
55
130
400
430
290
3
40
115
50
120
350
380
270
3
40
95
45
110
300
330
250
3
mA
mA
mA
mA
mA
mA
mA
mA
-
-
-
-
-
-
-
1
Note: 1. Enable on-chip refresh and address counters.
AC Operation Conditions & Timing Specification
AC Operation Conditions
Parameter
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
Input Different Voltage, CLK and CLK inputs
Input Crossing Point Voltage, CLK and CLK inputs
Symbol
V
IH
(AC)
V
IL
(AC)
V
ID
(AC)
V
IX
(AC)
Min
V
REF
+ 0.35
-
0.7
0.5*V
DDQ
-0.2
Max
-
V
REF
- 0.35
V
DDQ
+0.6
0.5*V
DDQ
+0.2
Unit
V
V
V
V
Note
-
-
1
2
Note: 1. V
ID
is the magnitude of the difference between the input level on CLK and the input on CLK .
2. The value of V
IX
is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the DC level of
the same.
Input / Output Capacitance
(V
DD
= 2.375V~2.625V, V
DDQ
=2.375V~2. 625V, T
A
= 25 °C , f = 1MHz)
(V
DD
= 2.5V~2.7V, V
DDQ
=2.5V~2.7V, T
A
= 25 °C , f = 1MHz (for speed -3.6))
Parameter
Input capacitance(A0~A11, BA0~BA1, CKE,
CS
,
RAS
,
CAS
,
WE
)
Symbol
C
IN1
C
IN2
C
OUT
C
IN3
Min
1
1
1
1
Max
4
5
6.5
6.5
Unit
pF
pF
pF
pF
Input capacitance (CLK, CLK )
Data & DQS input/output capacitance
Input capacitance (DM)
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2009
Revision : 2.3
5/50