欢迎访问ic37.com |
会员登录 免费注册
发布采购

M13S128324A-6LG 参数 Datasheet PDF下载

M13S128324A-6LG图片预览
型号: M13S128324A-6LG
PDF下载: 下载PDF文件 查看货源
内容描述: 1M ×32位×4银行双倍数据速率SDRAM [1M x 32 Bit x 4 Banks Double Data Rate SDRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 49 页 / 867 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
 浏览型号M13S128324A-6LG的Datasheet PDF文件第23页浏览型号M13S128324A-6LG的Datasheet PDF文件第24页浏览型号M13S128324A-6LG的Datasheet PDF文件第25页浏览型号M13S128324A-6LG的Datasheet PDF文件第26页浏览型号M13S128324A-6LG的Datasheet PDF文件第28页浏览型号M13S128324A-6LG的Datasheet PDF文件第29页浏览型号M13S128324A-6LG的Datasheet PDF文件第30页浏览型号M13S128324A-6LG的Datasheet PDF文件第31页  
ESMT  
M13S128324A  
Self Refresh  
A self refresh command is defines by having CS , RAS , CAS and CKE held low with WE high at the rising edge of the  
clock (CLK). Once the self refresh command is initiated, CKE must be held low to keep the device in self refresh mode. During  
the self refresh operation, all inputs except CKE are ignored. The clock is internally disabled during self refresh operation to  
reduce power consumption. The self refresh is exited by supplying stable clock input before returning CKE high, asserting  
deselect or NOP command and then asserting CKE high for longer than tXSRD for locking of DLL.  
C L K  
C L K  
Self  
Refresh  
Auto  
Refresh  
Rea d  
C O M M A N D  
CK E  
t X S N R  
t X S R  
D
Power down  
Power down is entered when CKE is registered low (no accesses can be in progress). If power-down occurs when all banks  
are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this  
mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CLK,  
CLK and CKE. For maximum power savings, the user has the option of disabling the DLL prior to entering power-down. In that  
case, the DLL must be enabled after exiting power-down, and 200 clock cycles must occur before a READ command can be  
issued. However, power-down duration is limited by the refresh requirements of the device, so in most applications, the  
self-refresh mode is preferred over the DLL disable power-down mode. In the power-down, CKE LOW and a stable clock signal  
must be maintained at the inputs of the DDR SDRAM, and all other input signals are “Don’t Care”. The power-down state is  
synchronously exited when CKE is registered HIGH (along with a NOP or DESELECT command). A valid executable command  
may be applied one clock cycle later.  
C L K  
C L K  
tIS  
tIS  
CK E  
VALID  
NOP  
C O M M A N D  
NOP  
VALID  
No column  
acess  
in program  
Enter power-down  
mode  
Exit power-down  
mode  
Elite Semiconductor Memory Technology Inc.  
Publication Date : May. 2007  
Revision : 1.8 27/49  
 复制成功!