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M13S128324A-6LG 参数 Datasheet PDF下载

M13S128324A-6LG图片预览
型号: M13S128324A-6LG
PDF下载: 下载PDF文件 查看货源
内容描述: 1M ×32位×4银行双倍数据速率SDRAM [1M x 32 Bit x 4 Banks Double Data Rate SDRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 49 页 / 867 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
M13S128324A  
Write with Auto Precharge  
If A8 is high when write command is issued, the write with auto-precharge function is performed. Any new command to the  
same bank should not be issued until the internal precharge is completed. The internal precharge begins after keeping  
tWR(min).  
<Burst Length = 4>  
0
1
2
3
4
5
6
7
8
C L K  
C L K  
Write  
Auto Precharge  
A
B a n k  
A
NO P  
NO P  
NO P  
NO P  
NO P  
NO P  
NO P  
C O M M A N D  
A C T I V E  
DQ S  
* B a n k c a n b e r e a c t i v a t e d a t  
c o m p l e t i o n o f t R P  
Dout 2  
Dout 1  
Dout 3  
Dout 0  
D Q ' s  
t W R  
t R P  
I n t e r n a l p r e c h a r g e s t a r t  
Auto Refresh & Self Refresh  
Auto Refresh  
An auto refresh command is issued by having CS , RAS and CAS held low with CKE and WE high at the rising edge  
of the clock(CLK). All banks must be precharged and idle for tRP(min) before the auto refresh command is applied. No control of  
the external address pins is requires once this cycle has started because of the internal address counter. When the refresh  
cycle has completed, all banks will be in the idle state. A delay between the auto refresh command and the next activate  
command or subsequent auto refresh command must be greater than or equal to the tRFC(min).  
C L K  
C L K  
Auto  
Refresh  
C O M M A N D  
PR E  
C M D  
CK E  
= Hi gh  
t R F C  
t R P  
Elite Semiconductor Memory Technology Inc.  
Publication Date : May. 2007  
Revision : 1.8  
26/49  
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