ESMT
M12S64322A
Page Write Cycle at Different Bank @ Burst Length = 4
0
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C L O C K
C K E
H I G H
C S
R A S
* N o t e 2
C A S
A D D R
R C c
CA a
R D d C C c
C D d
RA a
RB b
CB b
B A 1
B A 0
RB b
RA a
R D d
R C c
A10/AP
D Q
DBb3
D C c 0
DAa2
DAa0 DAa1
DBb2
CD d2
DAa3 DBb0 DBb1
tC D L
D C c 1 DD d0 DD d1
tR D L
W E
* N o t e 1
D Q M
W r i t e
( D - B a n k )
R o w A c t i v e
( D - B a n k )
W r i t e
( A - B a n k )
W r i t e
( B - B a n k )
R o w A c t i v e
( A - Bank )
P r e c h a r g e
( A l l B a n k s )
R o w A c t i v e
( B - B a n k )
W r i t e
( C - B a n k )
R o w A c t i v e
( C - B a n k )
:
D o n ' t c a r e
*Note : 1. To interrupt burst write by Row precharge , DQM should be asserted to mask invalid input data.
2. To interrupt burst write by Row precharge , both the write and the precharge banks must be the same.
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2007
Revision: 1.0 35/46